1===========================
2ARM64 CPU Feature Registers
3===========================
4
5Author: Suzuki K Poulose <suzuki.poulose@arm.com>
6
7
8This file describes the ABI for exporting the AArch64 CPU ID/feature
9registers to userspace. The availability of this ABI is advertised
10via the HWCAP_CPUID in HWCAPs.
11
121. Motivation
13-------------
14
15The ARM architecture defines a set of feature registers, which describe
16the capabilities of the CPU/system. Access to these system registers is
17restricted from EL0 and there is no reliable way for an application to
18extract this information to make better decisions at runtime. There is
19limited information available to the application via HWCAPs, however
20there are some issues with their usage.
21
22 a) Any change to the HWCAPs requires an update to userspace (e.g libc)
23    to detect the new changes, which can take a long time to appear in
24    distributions. Exposing the registers allows applications to get the
25    information without requiring updates to the toolchains.
26
27 b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
28    when ld is initialised at startup time).
29
30 c) HWCAPs cannot represent non-boolean information effectively. The
31    architecture defines a canonical format for representing features
32    in the ID registers; this is well defined and is capable of
33    representing all valid architecture variations.
34
35
362. Requirements
37---------------
38
39 a) Safety:
40
41    Applications should be able to use the information provided by the
42    infrastructure to run safely across the system. This has greater
43    implications on a system with heterogeneous CPUs.
44    The infrastructure exports a value that is safe across all the
45    available CPU on the system.
46
47    e.g, If at least one CPU doesn't implement CRC32 instructions, while
48    others do, we should report that the CRC32 is not implemented.
49    Otherwise an application could crash when scheduled on the CPU
50    which doesn't support CRC32.
51
52 b) Security:
53
54    Applications should only be able to receive information that is
55    relevant to the normal operation in userspace. Hence, some of the
56    fields are masked out(i.e, made invisible) and their values are set to
57    indicate the feature is 'not supported'. See Section 4 for the list
58    of visible features. Also, the kernel may manipulate the fields
59    based on what it supports. e.g, If FP is not supported by the
60    kernel, the values could indicate that the FP is not available
61    (even when the CPU provides it).
62
63 c) Implementation Defined Features
64
65    The infrastructure doesn't expose any register which is
66    IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
67
68 d) CPU Identification:
69
70    MIDR_EL1 is exposed to help identify the processor. On a
71    heterogeneous system, this could be racy (just like getcpu()). The
72    process could be migrated to another CPU by the time it uses the
73    register value, unless the CPU affinity is set. Hence, there is no
74    guarantee that the value reflects the processor that it is
75    currently executing on. The REVIDR is not exposed due to this
76    constraint, as REVIDR makes sense only in conjunction with the
77    MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
78    at::
79
80	/sys/devices/system/cpu/cpu$ID/regs/identification/
81	                                              \- midr
82	                                              \- revidr
83
843. Implementation
85--------------------
86
87The infrastructure is built on the emulation of the 'MRS' instruction.
88Accessing a restricted system register from an application generates an
89exception and ends up in SIGILL being delivered to the process.
90The infrastructure hooks into the exception handler and emulates the
91operation if the source belongs to the supported system register space.
92
93The infrastructure emulates only the following system register space::
94
95	Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
96
97(See Table C5-6 'System instruction encodings for non-Debug System
98register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
99registers).
100
101The following rules are applied to the value returned by the
102infrastructure:
103
104 a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
105 b) The value of a reserved field is populated with the reserved
106    value as defined by the architecture.
107 c) The value of a 'visible' field holds the system wide safe value
108    for the particular feature (except for MIDR_EL1, see section 4).
109 d) All other fields (i.e, invisible fields) are set to indicate
110    the feature is missing (as defined by the architecture).
111
1124. List of registers with visible features
113-------------------------------------------
114
115  1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
116
117     +------------------------------+---------+---------+
118     | Name                         |  bits   | visible |
119     +------------------------------+---------+---------+
120     | RNDR                         | [63-60] |    y    |
121     +------------------------------+---------+---------+
122     | TS                           | [55-52] |    y    |
123     +------------------------------+---------+---------+
124     | FHM                          | [51-48] |    y    |
125     +------------------------------+---------+---------+
126     | DP                           | [47-44] |    y    |
127     +------------------------------+---------+---------+
128     | SM4                          | [43-40] |    y    |
129     +------------------------------+---------+---------+
130     | SM3                          | [39-36] |    y    |
131     +------------------------------+---------+---------+
132     | SHA3                         | [35-32] |    y    |
133     +------------------------------+---------+---------+
134     | RDM                          | [31-28] |    y    |
135     +------------------------------+---------+---------+
136     | ATOMICS                      | [23-20] |    y    |
137     +------------------------------+---------+---------+
138     | CRC32                        | [19-16] |    y    |
139     +------------------------------+---------+---------+
140     | SHA2                         | [15-12] |    y    |
141     +------------------------------+---------+---------+
142     | SHA1                         | [11-8]  |    y    |
143     +------------------------------+---------+---------+
144     | AES                          | [7-4]   |    y    |
145     +------------------------------+---------+---------+
146
147
148  2) ID_AA64PFR0_EL1 - Processor Feature Register 0
149
150     +------------------------------+---------+---------+
151     | Name                         |  bits   | visible |
152     +------------------------------+---------+---------+
153     | DIT                          | [51-48] |    y    |
154     +------------------------------+---------+---------+
155     | SVE                          | [35-32] |    y    |
156     +------------------------------+---------+---------+
157     | GIC                          | [27-24] |    n    |
158     +------------------------------+---------+---------+
159     | AdvSIMD                      | [23-20] |    y    |
160     +------------------------------+---------+---------+
161     | FP                           | [19-16] |    y    |
162     +------------------------------+---------+---------+
163     | EL3                          | [15-12] |    n    |
164     +------------------------------+---------+---------+
165     | EL2                          | [11-8]  |    n    |
166     +------------------------------+---------+---------+
167     | EL1                          | [7-4]   |    n    |
168     +------------------------------+---------+---------+
169     | EL0                          | [3-0]   |    n    |
170     +------------------------------+---------+---------+
171
172
173  3) ID_AA64PFR1_EL1 - Processor Feature Register 1
174
175     +------------------------------+---------+---------+
176     | Name                         |  bits   | visible |
177     +------------------------------+---------+---------+
178     | MTE                          | [11-8]  |    y    |
179     +------------------------------+---------+---------+
180     | SSBS                         | [7-4]   |    y    |
181     +------------------------------+---------+---------+
182     | BT                           | [3-0]   |    y    |
183     +------------------------------+---------+---------+
184
185
186  4) MIDR_EL1 - Main ID Register
187
188     +------------------------------+---------+---------+
189     | Name                         |  bits   | visible |
190     +------------------------------+---------+---------+
191     | Implementer                  | [31-24] |    y    |
192     +------------------------------+---------+---------+
193     | Variant                      | [23-20] |    y    |
194     +------------------------------+---------+---------+
195     | Architecture                 | [19-16] |    y    |
196     +------------------------------+---------+---------+
197     | PartNum                      | [15-4]  |    y    |
198     +------------------------------+---------+---------+
199     | Revision                     | [3-0]   |    y    |
200     +------------------------------+---------+---------+
201
202   NOTE: The 'visible' fields of MIDR_EL1 will contain the value
203   as available on the CPU where it is fetched and is not a system
204   wide safe value.
205
206  5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
207
208     +------------------------------+---------+---------+
209     | Name                         |  bits   | visible |
210     +------------------------------+---------+---------+
211     | I8MM                         | [55-52] |    y    |
212     +------------------------------+---------+---------+
213     | DGH                          | [51-48] |    y    |
214     +------------------------------+---------+---------+
215     | BF16                         | [47-44] |    y    |
216     +------------------------------+---------+---------+
217     | SB                           | [39-36] |    y    |
218     +------------------------------+---------+---------+
219     | FRINTTS                      | [35-32] |    y    |
220     +------------------------------+---------+---------+
221     | GPI                          | [31-28] |    y    |
222     +------------------------------+---------+---------+
223     | GPA                          | [27-24] |    y    |
224     +------------------------------+---------+---------+
225     | LRCPC                        | [23-20] |    y    |
226     +------------------------------+---------+---------+
227     | FCMA                         | [19-16] |    y    |
228     +------------------------------+---------+---------+
229     | JSCVT                        | [15-12] |    y    |
230     +------------------------------+---------+---------+
231     | API                          | [11-8]  |    y    |
232     +------------------------------+---------+---------+
233     | APA                          | [7-4]   |    y    |
234     +------------------------------+---------+---------+
235     | DPB                          | [3-0]   |    y    |
236     +------------------------------+---------+---------+
237
238  6) ID_AA64MMFR0_EL1 - Memory model feature register 0
239
240     +------------------------------+---------+---------+
241     | Name                         |  bits   | visible |
242     +------------------------------+---------+---------+
243     | ECV                          | [63-60] |    y    |
244     +------------------------------+---------+---------+
245
246  7) ID_AA64MMFR2_EL1 - Memory model feature register 2
247
248     +------------------------------+---------+---------+
249     | Name                         |  bits   | visible |
250     +------------------------------+---------+---------+
251     | AT                           | [35-32] |    y    |
252     +------------------------------+---------+---------+
253
254  8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
255
256     +------------------------------+---------+---------+
257     | Name                         |  bits   | visible |
258     +------------------------------+---------+---------+
259     | F64MM                        | [59-56] |    y    |
260     +------------------------------+---------+---------+
261     | F32MM                        | [55-52] |    y    |
262     +------------------------------+---------+---------+
263     | I8MM                         | [47-44] |    y    |
264     +------------------------------+---------+---------+
265     | SM4                          | [43-40] |    y    |
266     +------------------------------+---------+---------+
267     | SHA3                         | [35-32] |    y    |
268     +------------------------------+---------+---------+
269     | BF16                         | [23-20] |    y    |
270     +------------------------------+---------+---------+
271     | BitPerm                      | [19-16] |    y    |
272     +------------------------------+---------+---------+
273     | AES                          | [7-4]   |    y    |
274     +------------------------------+---------+---------+
275     | SVEVer                       | [3-0]   |    y    |
276     +------------------------------+---------+---------+
277
278  8) ID_AA64MMFR1_EL1 - Memory model feature register 1
279
280     +------------------------------+---------+---------+
281     | Name                         |  bits   | visible |
282     +------------------------------+---------+---------+
283     | AFP                          | [47-44] |    y    |
284     +------------------------------+---------+---------+
285
286  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
287
288     +------------------------------+---------+---------+
289     | Name                         |  bits   | visible |
290     +------------------------------+---------+---------+
291     | MOPS                         | [19-16] |    y    |
292     +------------------------------+---------+---------+
293     | RPRES                        | [7-4]   |    y    |
294     +------------------------------+---------+---------+
295     | WFXT                         | [3-0]   |    y    |
296     +------------------------------+---------+---------+
297
298  10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
299
300     +------------------------------+---------+---------+
301     | Name                         |  bits   | visible |
302     +------------------------------+---------+---------+
303     | FPDP                         | [11-8]  |    y    |
304     +------------------------------+---------+---------+
305
306  11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
307
308     +------------------------------+---------+---------+
309     | Name                         |  bits   | visible |
310     +------------------------------+---------+---------+
311     | SIMDFMAC                     | [31-28] |    y    |
312     +------------------------------+---------+---------+
313     | SIMDSP                       | [19-16] |    y    |
314     +------------------------------+---------+---------+
315     | SIMDInt                      | [15-12] |    y    |
316     +------------------------------+---------+---------+
317     | SIMDLS                       | [11-8]  |    y    |
318     +------------------------------+---------+---------+
319
320  12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
321
322     +------------------------------+---------+---------+
323     | Name                         |  bits   | visible |
324     +------------------------------+---------+---------+
325     | CRC32                        | [19-16] |    y    |
326     +------------------------------+---------+---------+
327     | SHA2                         | [15-12] |    y    |
328     +------------------------------+---------+---------+
329     | SHA1                         | [11-8]  |    y    |
330     +------------------------------+---------+---------+
331     | AES                          | [7-4]   |    y    |
332     +------------------------------+---------+---------+
333
334
335Appendix I: Example
336-------------------
337
338::
339
340  /*
341   * Sample program to demonstrate the MRS emulation ABI.
342   *
343   * Copyright (C) 2015-2016, ARM Ltd
344   *
345   * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
346   *
347   * This program is free software; you can redistribute it and/or modify
348   * it under the terms of the GNU General Public License version 2 as
349   * published by the Free Software Foundation.
350   *
351   * This program is distributed in the hope that it will be useful,
352   * but WITHOUT ANY WARRANTY; without even the implied warranty of
353   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
354   * GNU General Public License for more details.
355   * This program is free software; you can redistribute it and/or modify
356   * it under the terms of the GNU General Public License version 2 as
357   * published by the Free Software Foundation.
358   *
359   * This program is distributed in the hope that it will be useful,
360   * but WITHOUT ANY WARRANTY; without even the implied warranty of
361   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
362   * GNU General Public License for more details.
363   */
364
365  #include <asm/hwcap.h>
366  #include <stdio.h>
367  #include <sys/auxv.h>
368
369  #define get_cpu_ftr(id) ({					\
370		unsigned long __val;				\
371		asm("mrs %0, "#id : "=r" (__val));		\
372		printf("%-20s: 0x%016lx\n", #id, __val);	\
373	})
374
375  int main(void)
376  {
377
378	if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
379		fputs("CPUID registers unavailable\n", stderr);
380		return 1;
381	}
382
383	get_cpu_ftr(ID_AA64ISAR0_EL1);
384	get_cpu_ftr(ID_AA64ISAR1_EL1);
385	get_cpu_ftr(ID_AA64MMFR0_EL1);
386	get_cpu_ftr(ID_AA64MMFR1_EL1);
387	get_cpu_ftr(ID_AA64PFR0_EL1);
388	get_cpu_ftr(ID_AA64PFR1_EL1);
389	get_cpu_ftr(ID_AA64DFR0_EL1);
390	get_cpu_ftr(ID_AA64DFR1_EL1);
391
392	get_cpu_ftr(MIDR_EL1);
393	get_cpu_ftr(MPIDR_EL1);
394	get_cpu_ftr(REVIDR_EL1);
395
396  #if 0
397	/* Unexposed register access causes SIGILL */
398	get_cpu_ftr(ID_MMFR0_EL1);
399  #endif
400
401	return 0;
402  }
403