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2Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
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4
5The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
6PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
7Cavium Coherent Processor Interconnect (CCPI2).
8
9The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
10Events are counted for the default channel (i.e. channel 0) and prorated
11to the total number of channels/tiles.
12
13The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
14counters. Counters are independently programmable to different events and
15can be started and stopped individually. None of the counters support an
16overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
18
19PMU UNCORE (perf) driver:
20
21The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22L3C devices.  Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
23(CCPI2) events simultaneously. The PMUs provide a description of their
24available events and configuration options under sysfs, see
25/sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
26
27The driver does not support sampling, therefore "perf record" will not
28work. Per-task perf sessions are also not supported.
29
30Examples::
31
32  # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
33
34  # perf stat -a -e \
35  uncore_dmc_0/cnt_cycles/,\
36  uncore_dmc_0/data_transfers/,\
37  uncore_dmc_0/read_txns/,\
38  uncore_dmc_0/write_txns/ sleep 1
39
40  # perf stat -a -e \
41  uncore_l3c_0/read_request/,\
42  uncore_l3c_0/read_hit/,\
43  uncore_l3c_0/inv_request/,\
44  uncore_l3c_0/inv_hit/ sleep 1
45