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2Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
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4
5The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
6PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC).
7
8The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
9Events are counted for the default channel (i.e. channel 0) and prorated
10to the total number of channels/tiles.
11
12The DMC and L3C support up to 4 counters. Counters are independently
13programmable and can be started and stopped individually. Each counter
14can be set to a different event. Counters are 32-bit and do not support
15an overflow interrupt; they are read every 2 seconds.
16
17PMU UNCORE (perf) driver:
18
19The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
20L3C devices.  Each PMU can be used to count up to 4 events
21simultaneously. The PMUs provide a description of their available events
22and configuration options under sysfs, see
23/sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id.
24
25The driver does not support sampling, therefore "perf record" will not
26work. Per-task perf sessions are also not supported.
27
28Examples::
29
30  # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
31
32  # perf stat -a -e \
33  uncore_dmc_0/cnt_cycles/,\
34  uncore_dmc_0/data_transfers/,\
35  uncore_dmc_0/read_txns/,\
36  uncore_dmc_0/write_txns/ sleep 1
37
38  # perf stat -a -e \
39  uncore_l3c_0/read_request/,\
40  uncore_l3c_0/read_hit/,\
41  uncore_l3c_0/inv_request/,\
42  uncore_l3c_0/inv_hit/ sleep 1
43