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2Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
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4
5There are no performance counters inside the DRAM controller, so performance
6signals are brought out to the edge of the controller where a set of 4 x 32 bit
7counters is implemented. This is controlled by the CSV modes programed in counter
8control register which causes a large number of PERF signals to be generated.
9
10Selection of the value for each counter is done via the config registers. There
11is one register for each counter. Counter 0 is special in that it always counts
12“time” and when expired causes a lock on itself and the other counters and an
13interrupt is raised. If any other counter overflows, it continues counting, and
14no interrupt is raised.
15
16The "format" directory describes format of the config (event ID) and config1
17(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
18devices/imx8_ddr0/format/. The "events" directory describes the events types
19hardware supported that can be used with perf tool, see /sys/bus/event_source/
20devices/imx8_ddr0/events/.
21  e.g.::
22        perf stat -a -e imx8_ddr0/cycles/ cmd
23        perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
24
25AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
26to count reading or writing matches filter setting. Filter setting is various
27from different DRAM controller implementations, which is distinguished by quirks
28in the driver.
29
30* With DDR_CAP_AXI_ID_FILTER quirk.
31  Filter is defined with two configuration parts:
32  --AXI_ID defines AxID matching value.
33  --AXI_MASKING defines which bits of AxID are meaningful for the matching.
34        0：corresponding bit is masked.
35        1: corresponding bit is not masked, i.e. used to do the matching.
36
37  AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
38  When non-masked bits are matching corresponding AXI_ID bits then counter is
39  incremented. Perf counter is incremented if
40          AxID && AXI_MASKING == AXI_ID && AXI_MASKING
41
42  This filter doesn't support filter different AXI ID for axid-read and axid-write
43  event at the same time as this filter is shared between counters.
44  e.g.::
45        perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
46        perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
47
48  NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
49  it will be reverted in driver automatically. so that the user can just specify
50  axi_id to monitor a specific id, rather than having to specify axi_mask.
51  e.g.::
52        perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
53