159809fe8SMauro Carvalho Chehab====================================================== 259809fe8SMauro Carvalho ChehabHiSilicon SoC uncore Performance Monitoring Unit (PMU) 359809fe8SMauro Carvalho Chehab====================================================== 459809fe8SMauro Carvalho Chehab 559809fe8SMauro Carvalho ChehabThe HiSilicon SoC chip includes various independent system device PMUs 659809fe8SMauro Carvalho Chehabsuch as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are 759809fe8SMauro Carvalho Chehabindependent and have hardware logic to gather statistics and performance 859809fe8SMauro Carvalho Chehabinformation. 959809fe8SMauro Carvalho Chehab 1059809fe8SMauro Carvalho ChehabThe HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster 1159809fe8SMauro Carvalho Chehab(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is 1259809fe8SMauro Carvalho Chehabcalled Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has 1359809fe8SMauro Carvalho Chehabtwo HHAs (0 - 1) and four DDRCs (0 - 3), respectively. 1459809fe8SMauro Carvalho Chehab 1559809fe8SMauro Carvalho ChehabHiSilicon SoC uncore PMU driver 1659809fe8SMauro Carvalho Chehab------------------------------- 1759809fe8SMauro Carvalho Chehab 1859809fe8SMauro Carvalho ChehabEach device PMU has separate registers for event counting, control and 1959809fe8SMauro Carvalho Chehabinterrupt, and the PMU driver shall register perf PMU drivers like L3C, 2059809fe8SMauro Carvalho ChehabHHA and DDRC etc. The available events and configuration options shall 2159809fe8SMauro Carvalho Chehabbe described in the sysfs, see: 2259809fe8SMauro Carvalho Chehab 2359809fe8SMauro Carvalho Chehab/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or 2459809fe8SMauro Carvalho Chehab/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>. 2559809fe8SMauro Carvalho ChehabThe "perf list" command shall list the available events from sysfs. 2659809fe8SMauro Carvalho Chehab 2759809fe8SMauro Carvalho ChehabEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU 2859809fe8SMauro Carvalho Chehabname will appear in event listing as hisi_sccl<sccl-id>_module<index-id>. 2959809fe8SMauro Carvalho Chehabwhere "sccl-id" is the identifier of the SCCL and "index-id" is the index of 3059809fe8SMauro Carvalho Chehabmodule. 3159809fe8SMauro Carvalho Chehab 3259809fe8SMauro Carvalho Chehabe.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in 3359809fe8SMauro Carvalho ChehabSCCL ID #3. 3459809fe8SMauro Carvalho Chehab 3559809fe8SMauro Carvalho Chehabe.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in 3659809fe8SMauro Carvalho ChehabSCCL ID #1. 3759809fe8SMauro Carvalho Chehab 3859809fe8SMauro Carvalho ChehabThe driver also provides a "cpumask" sysfs attribute, which shows the CPU core 3959809fe8SMauro Carvalho ChehabID used to count the uncore PMU event. 4059809fe8SMauro Carvalho Chehab 4159809fe8SMauro Carvalho ChehabExample usage of perf:: 4259809fe8SMauro Carvalho Chehab 4359809fe8SMauro Carvalho Chehab $# perf list 4459809fe8SMauro Carvalho Chehab hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] 4559809fe8SMauro Carvalho Chehab ------------------------------------------ 4659809fe8SMauro Carvalho Chehab hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] 4759809fe8SMauro Carvalho Chehab ------------------------------------------ 4859809fe8SMauro Carvalho Chehab hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] 4959809fe8SMauro Carvalho Chehab ------------------------------------------ 5059809fe8SMauro Carvalho Chehab hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] 5159809fe8SMauro Carvalho Chehab ------------------------------------------ 5259809fe8SMauro Carvalho Chehab 5359809fe8SMauro Carvalho Chehab $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 5459809fe8SMauro Carvalho Chehab $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 5559809fe8SMauro Carvalho Chehab 5659809fe8SMauro Carvalho ChehabThe current driver does not support sampling. So "perf record" is unsupported. 5759809fe8SMauro Carvalho ChehabAlso attach to a task is unsupported as the events are all uncore. 5859809fe8SMauro Carvalho Chehab 5959809fe8SMauro Carvalho ChehabNote: Please contact the maintainer for a complete list of events supported for 6059809fe8SMauro Carvalho Chehabthe PMU devices in the SoC and its information if needed. 61