1.. SPDX-License-Identifier: GPL-2.0
2
3=================
4PCI Test Function
5=================
6
7:Author: Kishon Vijay Abraham I <kishon@ti.com>
8
9Traditionally PCI RC has always been validated by using standard
10PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
11However with the addition of EP-core in linux kernel, it is possible
12to configure a PCI controller that can operate in EP mode to work as
13a test device.
14
15The PCI endpoint test device is a virtual device (defined in software)
16used to test the endpoint functionality and serve as a sample driver
17for other PCI endpoint devices (to use the EP framework).
18
19The PCI endpoint test device has the following registers:
20
21	1) PCI_ENDPOINT_TEST_MAGIC
22	2) PCI_ENDPOINT_TEST_COMMAND
23	3) PCI_ENDPOINT_TEST_STATUS
24	4) PCI_ENDPOINT_TEST_SRC_ADDR
25	5) PCI_ENDPOINT_TEST_DST_ADDR
26	6) PCI_ENDPOINT_TEST_SIZE
27	7) PCI_ENDPOINT_TEST_CHECKSUM
28	8) PCI_ENDPOINT_TEST_IRQ_TYPE
29	9) PCI_ENDPOINT_TEST_IRQ_NUMBER
30
31* PCI_ENDPOINT_TEST_MAGIC
32
33This register will be used to test BAR0. A known pattern will be written
34and read back from MAGIC register to verify BAR0.
35
36* PCI_ENDPOINT_TEST_COMMAND
37
38This register will be used by the host driver to indicate the function
39that the endpoint device must perform.
40
41========	================================================================
42Bitfield	Description
43========	================================================================
44Bit 0		raise legacy IRQ
45Bit 1		raise MSI IRQ
46Bit 2		raise MSI-X IRQ
47Bit 3		read command (read data from RC buffer)
48Bit 4		write command (write data to RC buffer)
49Bit 5		copy command (copy data from one RC buffer to another RC buffer)
50========	================================================================
51
52* PCI_ENDPOINT_TEST_STATUS
53
54This register reflects the status of the PCI endpoint device.
55
56========	==============================
57Bitfield	Description
58========	==============================
59Bit 0		read success
60Bit 1		read fail
61Bit 2		write success
62Bit 3		write fail
63Bit 4		copy success
64Bit 5		copy fail
65Bit 6		IRQ raised
66Bit 7		source address is invalid
67Bit 8		destination address is invalid
68========	==============================
69
70* PCI_ENDPOINT_TEST_SRC_ADDR
71
72This register contains the source address (RC buffer address) for the
73COPY/READ command.
74
75* PCI_ENDPOINT_TEST_DST_ADDR
76
77This register contains the destination address (RC buffer address) for
78the COPY/WRITE command.
79
80* PCI_ENDPOINT_TEST_IRQ_TYPE
81
82This register contains the interrupt type (Legacy/MSI) triggered
83for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
84
85Possible types:
86
87======	==
88Legacy	0
89MSI	1
90MSI-X	2
91======	==
92
93* PCI_ENDPOINT_TEST_IRQ_NUMBER
94
95This register contains the triggered ID interrupt.
96
97Admissible values:
98
99======	===========
100Legacy	0
101MSI	[1 .. 32]
102MSI-X	[1 .. 2048]
103======	===========
104