1*ee7abc10STamar MashiahWhat:		/sys/devices/platform/<platform>/etr3
2*ee7abc10STamar MashiahDate:		Apr 2021
3*ee7abc10STamar MashiahKernelVersion:	5.13
4*ee7abc10STamar MashiahContact:	"Tomas Winkler" <tomas.winkler@intel.com>
5*ee7abc10STamar MashiahDescription:
6*ee7abc10STamar Mashiah		The file exposes "Extended Test Mode Register 3" global
7*ee7abc10STamar Mashiah		reset bits. The bits are used during an Intel platform
8*ee7abc10STamar Mashiah		manufacturing process to indicate that consequent reset
9*ee7abc10STamar Mashiah		of the platform is a "global reset". This type of reset
10*ee7abc10STamar Mashiah		is required in order for manufacturing configurations
11*ee7abc10STamar Mashiah		to take effect.
12*ee7abc10STamar Mashiah
13*ee7abc10STamar Mashiah		Display global reset setting bits for PMC.
14*ee7abc10STamar Mashiah			* bit 31 - global reset is locked
15*ee7abc10STamar Mashiah			* bit 20 - global reset is set
16*ee7abc10STamar Mashiah		Writing bit 20 value to the etr3 will induce
17*ee7abc10STamar Mashiah		a platform "global reset" upon consequent platform reset,
18*ee7abc10STamar Mashiah		in case the register is not locked.
19*ee7abc10STamar Mashiah		The "global reset bit" should be locked on a production
20*ee7abc10STamar Mashiah		system and the file is in read-only mode.
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