1ee7abc10STamar MashiahWhat:		/sys/devices/platform/<platform>/etr3
2ee7abc10STamar MashiahDate:		Apr 2021
3ee7abc10STamar MashiahKernelVersion:	5.13
4ee7abc10STamar MashiahContact:	"Tomas Winkler" <tomas.winkler@intel.com>
5ee7abc10STamar MashiahDescription:
6ee7abc10STamar Mashiah		The file exposes "Extended Test Mode Register 3" global
7ee7abc10STamar Mashiah		reset bits. The bits are used during an Intel platform
8ee7abc10STamar Mashiah		manufacturing process to indicate that consequent reset
9ee7abc10STamar Mashiah		of the platform is a "global reset". This type of reset
10ee7abc10STamar Mashiah		is required in order for manufacturing configurations
11ee7abc10STamar Mashiah		to take effect.
12ee7abc10STamar Mashiah
13ee7abc10STamar Mashiah		Display global reset setting bits for PMC.
14*10317ddaSMauro Carvalho Chehab
15ee7abc10STamar Mashiah			* bit 31 - global reset is locked
16ee7abc10STamar Mashiah			* bit 20 - global reset is set
17*10317ddaSMauro Carvalho Chehab
18ee7abc10STamar Mashiah		Writing bit 20 value to the etr3 will induce
19ee7abc10STamar Mashiah		a platform "global reset" upon consequent platform reset,
20ee7abc10STamar Mashiah		in case the register is not locked.
21ee7abc10STamar Mashiah		The "global reset bit" should be locked on a production
22ee7abc10STamar Mashiah		system and the file is in read-only mode.
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