1What: /sys/bus/platform/devices/dfl-port.0/id 2Date: June 2018 3KernelVersion: 4.19 4Contact: Wu Hao <hao.wu@intel.com> 5Description: Read-only. It returns id of this port. One DFL FPGA device 6 may have more than one port. Userspace could use this id to 7 distinguish different ports under same FPGA device. 8 9What: /sys/bus/platform/devices/dfl-port.0/afu_id 10Date: June 2018 11KernelVersion: 4.19 12Contact: Wu Hao <hao.wu@intel.com> 13Description: Read-only. User can program different PR bitstreams to FPGA 14 Accelerator Function Unit (AFU) for different functions. It 15 returns uuid which could be used to identify which PR bitstream 16 is programmed in this AFU. 17