1What: /sys/class/habanalabs/hl<n>/armcp_kernel_ver 2Date: Jan 2019 3KernelVersion: 5.1 4Contact: oded.gabbay@gmail.com 5Description: Version of the Linux kernel running on the device's CPU. 6 Will be DEPRECATED in Linux kernel version 5.10, and be 7 replaced with cpucp_kernel_ver 8 9What: /sys/class/habanalabs/hl<n>/armcp_ver 10Date: Jan 2019 11KernelVersion: 5.1 12Contact: oded.gabbay@gmail.com 13Description: Version of the application running on the device's CPU 14 Will be DEPRECATED in Linux kernel version 5.10, and be 15 replaced with cpucp_ver 16 17What: /sys/class/habanalabs/hl<n>/clk_max_freq_mhz 18Date: Jun 2019 19KernelVersion: not yet upstreamed 20Contact: oded.gabbay@gmail.com 21Description: Allows the user to set the maximum clock frequency, in MHz. 22 The device clock might be set to lower value than the maximum. 23 The user should read the clk_cur_freq_mhz to see the actual 24 frequency value of the device clock. This property is valid 25 only for the Gaudi ASIC family 26 27What: /sys/class/habanalabs/hl<n>/clk_cur_freq_mhz 28Date: Jun 2019 29KernelVersion: not yet upstreamed 30Contact: oded.gabbay@gmail.com 31Description: Displays the current frequency, in MHz, of the device clock. 32 This property is valid only for the Gaudi ASIC family 33 34What: /sys/class/habanalabs/hl<n>/cpld_ver 35Date: Jan 2019 36KernelVersion: 5.1 37Contact: oded.gabbay@gmail.com 38Description: Version of the Device's CPLD F/W 39 40What: /sys/class/habanalabs/hl<n>/cpucp_kernel_ver 41Date: Oct 2020 42KernelVersion: 5.10 43Contact: oded.gabbay@gmail.com 44Description: Version of the Linux kernel running on the device's CPU 45 46What: /sys/class/habanalabs/hl<n>/cpucp_ver 47Date: Oct 2020 48KernelVersion: 5.10 49Contact: oded.gabbay@gmail.com 50Description: Version of the application running on the device's CPU 51 52What: /sys/class/habanalabs/hl<n>/device_type 53Date: Jan 2019 54KernelVersion: 5.1 55Contact: oded.gabbay@gmail.com 56Description: Displays the code name of the device according to its type. 57 The supported values are: "GOYA" 58 59What: /sys/class/habanalabs/hl<n>/eeprom 60Date: Jan 2019 61KernelVersion: 5.1 62Contact: oded.gabbay@gmail.com 63Description: A binary file attribute that contains the contents of the 64 on-board EEPROM 65 66What: /sys/class/habanalabs/hl<n>/fuse_ver 67Date: Jan 2019 68KernelVersion: 5.1 69Contact: oded.gabbay@gmail.com 70Description: Displays the device's version from the eFuse 71 72What: /sys/class/habanalabs/hl<n>/hard_reset 73Date: Jan 2019 74KernelVersion: 5.1 75Contact: oded.gabbay@gmail.com 76Description: Interface to trigger a hard-reset operation for the device. 77 Hard-reset will reset ALL internal components of the device 78 except for the PCI interface and the internal PLLs 79 80What: /sys/class/habanalabs/hl<n>/hard_reset_cnt 81Date: Jan 2019 82KernelVersion: 5.1 83Contact: oded.gabbay@gmail.com 84Description: Displays how many times the device have undergone a hard-reset 85 operation since the driver was loaded 86 87What: /sys/class/habanalabs/hl<n>/high_pll 88Date: Jan 2019 89KernelVersion: 5.1 90Contact: oded.gabbay@gmail.com 91Description: Allows the user to set the maximum clock frequency for MME, TPC 92 and IC when the power management profile is set to "automatic". 93 This property is valid only for the Goya ASIC family 94 95What: /sys/class/habanalabs/hl<n>/ic_clk 96Date: Jan 2019 97KernelVersion: 5.1 98Contact: oded.gabbay@gmail.com 99Description: Allows the user to set the maximum clock frequency, in Hz, of 100 the Interconnect fabric. Writes to this parameter affect the 101 device only when the power management profile is set to "manual" 102 mode. The device IC clock might be set to lower value than the 103 maximum. The user should read the ic_clk_curr to see the actual 104 frequency value of the IC. This property is valid only for the 105 Goya ASIC family 106 107What: /sys/class/habanalabs/hl<n>/ic_clk_curr 108Date: Jan 2019 109KernelVersion: 5.1 110Contact: oded.gabbay@gmail.com 111Description: Displays the current clock frequency, in Hz, of the Interconnect 112 fabric. This property is valid only for the Goya ASIC family 113 114What: /sys/class/habanalabs/hl<n>/infineon_ver 115Date: Jan 2019 116KernelVersion: 5.1 117Contact: oded.gabbay@gmail.com 118Description: Version of the Device's power supply F/W code 119 120What: /sys/class/habanalabs/hl<n>/max_power 121Date: Jan 2019 122KernelVersion: 5.1 123Contact: oded.gabbay@gmail.com 124Description: Allows the user to set the maximum power consumption of the 125 device in milliwatts. 126 127What: /sys/class/habanalabs/hl<n>/mme_clk 128Date: Jan 2019 129KernelVersion: 5.1 130Contact: oded.gabbay@gmail.com 131Description: Allows the user to set the maximum clock frequency, in Hz, of 132 the MME compute engine. Writes to this parameter affect the 133 device only when the power management profile is set to "manual" 134 mode. The device MME clock might be set to lower value than the 135 maximum. The user should read the mme_clk_curr to see the actual 136 frequency value of the MME. This property is valid only for the 137 Goya ASIC family 138 139What: /sys/class/habanalabs/hl<n>/mme_clk_curr 140Date: Jan 2019 141KernelVersion: 5.1 142Contact: oded.gabbay@gmail.com 143Description: Displays the current clock frequency, in Hz, of the MME compute 144 engine. This property is valid only for the Goya ASIC family 145 146What: /sys/class/habanalabs/hl<n>/pci_addr 147Date: Jan 2019 148KernelVersion: 5.1 149Contact: oded.gabbay@gmail.com 150Description: Displays the PCI address of the device. This is needed so the 151 user would be able to open a device based on its PCI address 152 153What: /sys/class/habanalabs/hl<n>/pm_mng_profile 154Date: Jan 2019 155KernelVersion: 5.1 156Contact: oded.gabbay@gmail.com 157Description: Power management profile. Values are "auto", "manual". In "auto" 158 mode, the driver will set the maximum clock frequency to a high 159 value when a user-space process opens the device's file (unless 160 it was already opened by another process). The driver will set 161 the max clock frequency to a low value when there are no user 162 processes that are opened on the device's file. In "manual" 163 mode, the user sets the maximum clock frequency by writing to 164 ic_clk, mme_clk and tpc_clk. This property is valid only for 165 the Goya ASIC family 166 167What: /sys/class/habanalabs/hl<n>/preboot_btl_ver 168Date: Jan 2019 169KernelVersion: 5.1 170Contact: oded.gabbay@gmail.com 171Description: Version of the device's preboot F/W code 172 173What: /sys/class/habanalabs/hl<n>/soft_reset 174Date: Jan 2019 175KernelVersion: 5.1 176Contact: oded.gabbay@gmail.com 177Description: Interface to trigger a soft-reset operation for the device. 178 Soft-reset will reset only the compute and DMA engines of the 179 device 180 181What: /sys/class/habanalabs/hl<n>/soft_reset_cnt 182Date: Jan 2019 183KernelVersion: 5.1 184Contact: oded.gabbay@gmail.com 185Description: Displays how many times the device have undergone a soft-reset 186 operation since the driver was loaded 187 188What: /sys/class/habanalabs/hl<n>/status 189Date: Jan 2019 190KernelVersion: 5.1 191Contact: oded.gabbay@gmail.com 192Description: Status of the card: "Operational", "Malfunction", "In reset". 193 194What: /sys/class/habanalabs/hl<n>/thermal_ver 195Date: Jan 2019 196KernelVersion: 5.1 197Contact: oded.gabbay@gmail.com 198Description: Version of the Device's thermal daemon 199 200What: /sys/class/habanalabs/hl<n>/tpc_clk 201Date: Jan 2019 202KernelVersion: 5.1 203Contact: oded.gabbay@gmail.com 204Description: Allows the user to set the maximum clock frequency, in Hz, of 205 the TPC compute engines. Writes to this parameter affect the 206 device only when the power management profile is set to "manual" 207 mode. The device TPC clock might be set to lower value than the 208 maximum. The user should read the tpc_clk_curr to see the actual 209 frequency value of the TPC. This property is valid only for 210 Goya ASIC family 211 212What: /sys/class/habanalabs/hl<n>/tpc_clk_curr 213Date: Jan 2019 214KernelVersion: 5.1 215Contact: oded.gabbay@gmail.com 216Description: Displays the current clock frequency, in Hz, of the TPC compute 217 engines. This property is valid only for the Goya ASIC family 218 219What: /sys/class/habanalabs/hl<n>/uboot_ver 220Date: Jan 2019 221KernelVersion: 5.1 222Contact: oded.gabbay@gmail.com 223Description: Version of the u-boot running on the device's CPU