1a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune 2a7112b74SYicong YangDate: October 2022 3a7112b74SYicong YangKernelVersion: 6.1 4a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 5a7112b74SYicong YangDescription: This directory contains files for tuning the PCIe link 6a7112b74SYicong Yang parameters(events). Each file is named after the event 7a7112b74SYicong Yang of the PCIe link. 8a7112b74SYicong Yang 9a7112b74SYicong Yang See Documentation/trace/hisi-ptt.rst for more information. 10a7112b74SYicong Yang 11a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl 12a7112b74SYicong YangDate: October 2022 13a7112b74SYicong YangKernelVersion: 6.1 14a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 15a7112b74SYicong YangDescription: (RW) Controls the weight of Tx completion TLPs, which influence 16a7112b74SYicong Yang the proportion of outbound completion TLPs on the PCIe link. 17a7112b74SYicong Yang The available tune data is [0, 1, 2]. Writing a negative value 18a7112b74SYicong Yang will return an error, and out of range values will be converted 19a7112b74SYicong Yang to 2. The value indicates a probable level of the event. 20a7112b74SYicong Yang 21a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np 22a7112b74SYicong YangDate: October 2022 23a7112b74SYicong YangKernelVersion: 6.1 24a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 25a7112b74SYicong YangDescription: (RW) Controls the weight of Tx non-posted TLPs, which influence 26a7112b74SYicong Yang the proportion of outbound non-posted TLPs on the PCIe link. 27a7112b74SYicong Yang The available tune data is [0, 1, 2]. Writing a negative value 28a7112b74SYicong Yang will return an error, and out of range values will be converted 29a7112b74SYicong Yang to 2. The value indicates a probable level of the event. 30a7112b74SYicong Yang 31a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p 32a7112b74SYicong YangDate: October 2022 33a7112b74SYicong YangKernelVersion: 6.1 34a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 35a7112b74SYicong YangDescription: (RW) Controls the weight of Tx posted TLPs, which influence the 36a7112b74SYicong Yang proportion of outbound posted TLPs on the PCIe link. 37a7112b74SYicong Yang The available tune data is [0, 1, 2]. Writing a negative value 38a7112b74SYicong Yang will return an error, and out of range values will be converted 39a7112b74SYicong Yang to 2. The value indicates a probable level of the event. 40a7112b74SYicong Yang 41a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level 42a7112b74SYicong YangDate: October 2022 43a7112b74SYicong YangKernelVersion: 6.1 44a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 45a7112b74SYicong YangDescription: (RW) Control the allocated buffer watermark for inbound packets. 46a7112b74SYicong Yang The packets will be stored in the buffer first and then transmitted 47a7112b74SYicong Yang either when the watermark reached or when timed out. 48a7112b74SYicong Yang The available tune data is [0, 1, 2]. Writing a negative value 49a7112b74SYicong Yang will return an error, and out of range values will be converted 50a7112b74SYicong Yang to 2. The value indicates a probable level of the event. 51a7112b74SYicong Yang 52a7112b74SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level 53a7112b74SYicong YangDate: October 2022 54a7112b74SYicong YangKernelVersion: 6.1 55a7112b74SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 56a7112b74SYicong YangDescription: (RW) Control the allocated buffer watermark of outbound packets. 57a7112b74SYicong Yang The packets will be stored in the buffer first and then transmitted 58a7112b74SYicong Yang either when the watermark reached or when timed out. 59a7112b74SYicong Yang The available tune data is [0, 1, 2]. Writing a negative value 60a7112b74SYicong Yang will return an error, and out of range values will be converted 61a7112b74SYicong Yang to 2. The value indicates a probable level of the event. 62*6373c463SYicong Yang 63*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters 64*6373c463SYicong YangDate: May 2023 65*6373c463SYicong YangKernelVersion: 6.5 66*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 67*6373c463SYicong YangDescription: This directory contains the files providing the PCIe Root Port filters 68*6373c463SYicong Yang information used for PTT trace. Each file is named after the supported 69*6373c463SYicong Yang Root Port device name <domain>:<bus>:<device>.<function>. 70*6373c463SYicong Yang 71*6373c463SYicong Yang See the description of the "filter" in Documentation/trace/hisi-ptt.rst 72*6373c463SYicong Yang for more information. 73*6373c463SYicong Yang 74*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/multiselect 75*6373c463SYicong YangDate: May 2023 76*6373c463SYicong YangKernelVersion: 6.5 77*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 78*6373c463SYicong YangDescription: (Read) Indicates if this kind of filter can be selected at the same 79*6373c463SYicong Yang time as others filters, or must be used on it's own. 1 indicates 80*6373c463SYicong Yang the former case and 0 indicates the latter. 81*6373c463SYicong Yang 82*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/<bdf> 83*6373c463SYicong YangDate: May 2023 84*6373c463SYicong YangKernelVersion: 6.5 85*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 86*6373c463SYicong YangDescription: (Read) Indicates the filter value of this Root Port filter, which 87*6373c463SYicong Yang can be used to control the TLP headers to trace by the PTT trace. 88*6373c463SYicong Yang 89*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters 90*6373c463SYicong YangDate: May 2023 91*6373c463SYicong YangKernelVersion: 6.5 92*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 93*6373c463SYicong YangDescription: This directory contains the files providing the PCIe Requester filters 94*6373c463SYicong Yang information used for PTT trace. Each file is named after the supported 95*6373c463SYicong Yang Endpoint device name <domain>:<bus>:<device>.<function>. 96*6373c463SYicong Yang 97*6373c463SYicong Yang See the description of the "filter" in Documentation/trace/hisi-ptt.rst 98*6373c463SYicong Yang for more information. 99*6373c463SYicong Yang 100*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/multiselect 101*6373c463SYicong YangDate: May 2023 102*6373c463SYicong YangKernelVersion: 6.5 103*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 104*6373c463SYicong YangDescription: (Read) Indicates if this kind of filter can be selected at the same 105*6373c463SYicong Yang time as others filters, or must be used on it's own. 1 indicates 106*6373c463SYicong Yang the former case and 0 indicates the latter. 107*6373c463SYicong Yang 108*6373c463SYicong YangWhat: /sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/<bdf> 109*6373c463SYicong YangDate: May 2023 110*6373c463SYicong YangKernelVersion: 6.5 111*6373c463SYicong YangContact: Yicong Yang <yangyicong@hisilicon.com> 112*6373c463SYicong YangDescription: (Read) Indicates the filter value of this Requester filter, which 113*6373c463SYicong Yang can be used to control the TLP headers to trace by the PTT trace. 114