1What:		/sys/bus/coresight/devices/<memory_map>.etb/enable_sink
2Date:		November 2014
3KernelVersion:	3.19
4Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
5Description:	(RW) Add/remove a sink from a trace path.  There can be multiple
6		source for a single sink.
7		ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
8
9What:		/sys/bus/coresight/devices/<memory_map>.etb/status
10Date:		November 2014
11KernelVersion:	3.19
12Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
13Description:	(R) List various control and status registers.  The specific
14		layout and content is driver specific.
15
16What:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
17Date:		November 2014
18KernelVersion:	3.19
19Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
20Description:	(RW) Disables write access to the Trace RAM by stopping the
21		formatter after a defined number of words have been stored
22		following the trigger event. The number of 32-bit words written
23		into the Trace RAM following the trigger event is equal to the
24		value stored in this register+1 (from ARM ETB-TRM).
25