1What:		/sys/bus/coresight/devices/<memory_map>.etb/enable_sink
2Date:		November 2014
3KernelVersion:	3.19
4Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
5Description:	(RW) Add/remove a sink from a trace path.  There can be multiple
6		source for a single sink.
7		ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
8
9What:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
10Date:		November 2014
11KernelVersion:	3.19
12Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
13Description:	(RW) Disables write access to the Trace RAM by stopping the
14		formatter after a defined number of words have been stored
15		following the trigger event. The number of 32-bit words written
16		into the Trace RAM following the trigger event is equal to the
17		value stored in this register+1 (from ARM ETB-TRM).
18
19What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
20Date:		March 2016
21KernelVersion:	4.7
22Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
23Description:	(R) Defines the depth, in words, of the trace RAM in powers of
24		2.  The value is read directly from HW register RDP, 0x004.
25
26What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
27Date:		March 2016
28KernelVersion:	4.7
29Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
30Description:	(R) Shows the value held by the ETB status register.  The value
31		is read directly from HW register STS, 0x00C.
32
33What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
34Date:		March 2016
35KernelVersion:	4.7
36Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
37Description:	(R) Shows the value held by the ETB RAM Read Pointer register
38		that is used to read entries from the Trace RAM over the APB
39		interface.  The value is read directly from HW register RRP,
40		0x014.
41
42What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
43Date:		March 2016
44KernelVersion:	4.7
45Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
46Description:	(R) Shows the value held by the ETB RAM Write Pointer register
47		that is used to sets the write pointer to write entries from
48		the CoreSight bus into the Trace RAM. The value is read directly
49		from HW register RWP, 0x018.
50
51What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
52Date:		March 2016
53KernelVersion:	4.7
54Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
55Description:	(R) Similar to "trigger_cntr" above except that this value is
56		read directly from HW register TRG, 0x01C.
57
58What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
59Date:		March 2016
60KernelVersion:	4.7
61Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
62Description:	(R) Shows the value held by the ETB Control register. The value
63		is read directly from HW register CTL, 0x020.
64
65What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
66Date:		March 2016
67KernelVersion:	4.7
68Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
69Description:	(R) Shows the value held by the ETB Formatter and Flush Status
70		register.  The value is read directly from HW register FFSR,
71		0x300.
72
73What:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
74Date:		March 2016
75KernelVersion:	4.7
76Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
77Description:	(R) Shows the value held by the ETB Formatter and Flush Control
78		register.  The value is read directly from HW register FFCR,
79		0x304.
80