1What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 2Date: November 2014 3KernelVersion: 3.19 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Add/remove a sink from a trace path. There can be multiple 6 source for a single sink. 7 8 ex:: 9 10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 11 12What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 13Date: November 2014 14KernelVersion: 3.19 15Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 16Description: (RW) Disables write access to the Trace RAM by stopping the 17 formatter after a defined number of words have been stored 18 following the trigger event. The number of 32-bit words written 19 into the Trace RAM following the trigger event is equal to the 20 value stored in this register+1 (from ARM ETB-TRM). 21 22What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 23Date: March 2016 24KernelVersion: 4.7 25Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 26Description: (Read) Defines the depth, in words, of the trace RAM in powers of 27 2. The value is read directly from HW register RDP, 0x004. 28 29What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 30Date: March 2016 31KernelVersion: 4.7 32Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 33Description: (Read) Shows the value held by the ETB status register. The value 34 is read directly from HW register STS, 0x00C. 35 36What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 37Date: March 2016 38KernelVersion: 4.7 39Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 40Description: (Read) Shows the value held by the ETB RAM Read Pointer register 41 that is used to read entries from the Trace RAM over the APB 42 interface. The value is read directly from HW register RRP, 43 0x014. 44 45What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 46Date: March 2016 47KernelVersion: 4.7 48Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 49Description: (Read) Shows the value held by the ETB RAM Write Pointer register 50 that is used to sets the write pointer to write entries from 51 the CoreSight bus into the Trace RAM. The value is read directly 52 from HW register RWP, 0x018. 53 54What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 55Date: March 2016 56KernelVersion: 4.7 57Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 58Description: (Read) Similar to "trigger_cntr" above except that this value is 59 read directly from HW register TRG, 0x01C. 60 61What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 62Date: March 2016 63KernelVersion: 4.7 64Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 65Description: (Read) Shows the value held by the ETB Control register. The value 66 is read directly from HW register CTL, 0x020. 67 68What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 69Date: March 2016 70KernelVersion: 4.7 71Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 72Description: (Read) Shows the value held by the ETB Formatter and Flush Status 73 register. The value is read directly from HW register FFSR, 74 0x300. 75 76What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 77Date: March 2016 78KernelVersion: 4.7 79Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 80Description: (Read) Shows the value held by the ETB Formatter and Flush Control 81 register. The value is read directly from HW register FFCR, 82 0x304. 83