1# Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC Systems 2 3## Scope 4 5This design provides an efficient method to transfer MCTP packets between the 6host and BMC over the LPC bus on ASPEED BMC platforms. 7 8## References 9 10The following referenced documents are indispensable for the application of 11this document. 12 131. DMTF DSP0236, Management Component Transport Protocol (MCTP) Base 14Specification 1.0, 15http://www.dmtf.org/standards/published_documents/DSP0236_1.0.pdf 16 172. Intel (R) Low Pin Count (LPC) Interface Specification 1.1, 18https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf 19 203. IPMI Consortium, Intelligent Platform Management Interface Specification, 21v1.5 Revision 1.1 February 20, 2002, 22http://download.intel.com/design/servers/ipmi/IPMIv1_5rev1_1.pdf 23 24## Definitions 25 26**BTU: Baseline Transmission Unit** 27 28Defined by the MCTP base specification as the smallest maximum packet size all 29MCTP-compliant endpoints must accept. 30 31**IBF: Input Buffer Full** 32 33A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF 34flag indicates that a value has been written by the host to the corresponding 35Input Data Register (IDR). 36 37**IDR: Input Data Register** 38 39One of the three register interfaces exposed by a KCS device. The IDR is a one 40byte buffer which is written by the host and read by the BMC. 41 42**KCS: Keyboard-Controller-Style** 43 44A set of bit definitions and operation of the registers typically used in 45keyboard microcontrollers and embedded controllers. The term "Keyboard 46Controller Style" reflects that the register definition was originally used as 47the legacy "8742" keyboard controller interface in PC architecture computer 48systems. This interface is available built-in to several commercially 49available microcontrollers. Data is transferred across the KCS interface using 50a per-byte handshake. 51 52**LPC Bus: Low Pin Count Bus** 53 54A bus specification that implements ISA bus in a reduced physical form while 55extending ISA's capabilities. 56 57**LPC FW: LPC Firmware Cycles** 58 59LPC firmware cycles allow separate boot BIOS firmware memory cycles and 60application memory cycles with respect to the LPC bus. The ASPEED BMCs allow 61remapping of the LPC firmware cycles onto arbitrary regions of the BMC's 62physical address space, including RAM. 63 64**MTU: Maximum Transmission Unit** 65 66The largest payload the link will accept for a packet. The Maximum Transmission 67Unit represents a value that is at least as large as the BTU. Negotiation of 68MTU values larger than the BTU may improve throughput for data-intensive 69transfers. 70 71**OBF: Output Buffer Full** 72 73A hardware-defined flag bit in a KCS device's Status Register (STR). The OBF 74flag indicates that a value has been written by the BMC to the corresponding 75Output Data Register (ODR). 76 77**ODR: Output Data Register** 78 79One of the three register interfaces exposed by a KCS device. The ODR is a 80one byte buffer which is written by the BMC and read by the host. 81 82**STR: Status Register** 83 84One of the three register interfaces exposed by a KCS device. STR is a 85BMC-controlled, eight-bit register exposed to both the BMC and the host for 86indication of IBF and OBF events on the input (IDR) and output (ODR) buffers. 87Bits that are not defined by hardware can be software-controlled in a manner 88defined by a platform-specific ABI. 89 90## Conventions 91 92Where unspecified, state, command and sequence descriptions apply to all 93versions of the protocol unless marked otherwise. 94 95## MCTP over LPC Transport 96 97### Concepts 98 99The basic components used for the transfer are: 100 101* An interrupt mechanism using the IPMI KCS interface 102* A window of the LPC FW address space, where reads and writes are forwarded to 103 BMC memory, using the LPC2AHB hardware 104 105In order to transfer a packet, either side of the channel (BMC or host) will: 106 1071. Write the packet to the LPC FW window 108 * The BMC will perform writes by writing to the memory backing the LPC 109 window 110 * The host will perform writes by writing to the LPC bus, at predefined 111 addresses 1122. Trigger an interrupt on the remote side, by writing to the KCS data buffer 113 114On this indication, the remote side will: 115 1161. Read from the KCS status register, which shows that the single-byte KCS data 117 buffer is full 1182. Read the MCTP packet from the LPC FW window 1193. Read from the KCS buffer, to clear the 'buffer full' state. 120 121### Scope 122 123The document limits itself to describing the operation of the binding protocol. 124The following issues of protocol ABI are considered out of scope: 125 1261. The LPC IO address and Serial IRQ parameters of the KCS device 1272. The concrete location of the control region in the LPC FW address space 128 129### KCS Interface 130 131The KCS hardware on the ASPEED BMCs is used as a method of indicating, to the 132remote side, that a packet is ready to be transferred through the LPC FW 133mapping. 134 135The KCS hardware consists of two single-byte buffers: the Output Data Register 136(ODR) and the Input Data Register (IDR). The ODR is written by the BMC and read 137by the host. The IDR is the obverse. 138 139The KCS unit also contains a status register (STR), allowing both host and BMC 140to determine if there is data in the ODR or IDR. These are single-bit flags, 141designated Input/Output Buffer Full (IBF/OBF), and are automatically set by 142hardware when data has been written to the corresponding ODR/IDR buffer (and 143cleared when data has been read). 144 145While the IBF and OBF flags are managed in hardware, the remaining 146software-defined bits in the status register are used to carry other required 147protocol state. A problematic feature of the KCS status register is described 148in the IPMI specification, which states that an interrupt may be triggered on 149writes to the KCS status register but hardware implementations are not required 150to do so. Comparatively, writes to the data registers must set the 151corresponding buffer-full flag and invoke an interrupt. 152 153To ensure interrupts are generated for status updates, we exploit the OBF 154interrupt to signal a status update by writing a dummy command to ODR after 155updating the status register, as outlined below. 156 157### LPC FW Window 158 159The window of BMC-memory-backed LPC FW address space has a predefined format, 160consisting of: 161 162* A control descriptor, describing static data about the rest of the window 163* A receive area for BMC-to-host packets 164* A transmit area, for host-to-BMC packets 165 166The control descriptor contains a version, and offset and size data for the 167transmit and receive areas. These offsets are relative to the start of the LPC 168FW window. 169 170Full definition of the control area is defined below, and it will be the base 171for all future versions. 172 173``` 174struct mctp_lpcmap_hdr { 175 uint32_t magic; 176 177 uint16_t bmc_ver_min; 178 uint16_t bmc_ver_cur; 179 uint16_t host_ver_min; 180 uint16_t host_ver_cur; 181 uint16_t negotiated_ver; 182 uint16_t pad0; 183 184 uint32_t rx_offset; 185 uint32_t rx_size; 186 uint32_t tx_offset; 187 uint32_t tx_size; 188} __attribute__((packed)); 189``` 190 191Where the magic value marking the beginning of the control area is the ASCII 192encoding of "MCTP": 193 194``` 195#define LPC_MAGIC 0x4d435450 196``` 197 198The transmit and receive areas contain a length field, followed by the actual 199MCTP packet to be transferred. At version 1, only a single MCTP packet is 200present in the Rx and Tx areas. This may change for future versions of the 201protocol. 202 203All control data is in big-endian format. MCTP packet data is transferred 204exactly as is presented, and no data escaping is performed. 205 206#### Negotiation of the Maximum Transmission Unit 207 208Version 1 of the protocol offers no mechanism for negotiation of the maximum 209transmission unit. The Rx and Tx buffers must be sized to accommodate packets 210up to the Baseline Transmission Unit, and the implementation assumes that the 211MTU is set to the BTU regardless of the values of `rx_size` and `tx_size`. 212 213Version 2 of the protocol exploits the `rx_size` and `tx_size` fields in the 214control region to negotiate the link MTU. Note that at the time that the MTU is 215under negotiation the protocol version has not been finalised, so the process 216is necessarily backwards-compatible. 217 218The relevant property that each endpoint must control is the MTU of packets it 219will receive, as this governs how the remote endpoint's packetisation impacts 220memory pressure at the local endpoint. As such while the BMC MUST populate 221`rx_size` for backwards compatibility with version 1, the host MAY write 222`rx_size` without regard for its current value if the host supports version 2. 223The BMC controls the value of `tx_size`, and MAY choose to adjust it in 224response to the host's proposed `rx_size` value. As such, when `Channel Active` 225is set by the BMC, the host MUST read both `rx_size` and `tx_size` in response 226to ensure both the BMC and the host have a consistent understanding of the MTU 227in each direction. It is convention for `rx_size` and `tx_size` to be set to 228the same value by the BMC as part of finalising the channel, though it is not 229invalid to have asymmetric MTUs. 230 231For all protocol versions, the following properties must be upheld for the Rx 232and Tx buffers to be considered valid: 233 234* Intersect neither eachother nor the control region 235* Not extend beyond the window allocated to MCTP in the LPC FW address space 236* Must accommodate at least BTU-sized payloads 237 238The BMC MAY choose to fail channel initialisation if these properties are 239violated in the negotiation process. 240 241### KCS Status and Control Sequences 242 243The KCS status flags and command set govern the state of the protocol, defining 244the ability to send and receive packets on the LPC bus. 245 246#### KCS Status Register Layout 247 248| Bit | Managed By | Description | 249|-----|------------|-------------| 250| 7 | Software | (MSB) BMC Active | 251| 6 | Software | Channel active, version negotiated | 252| 5 | Software | Unused | 253| 4 | Software | Unused | 254| 3 | Hardware | Command / Data | 255| 2 | Software | Unused | 256| 1 | Hardware | Input Buffer Full | 257| 0 | Hardware | (LSB) Output Buffer Full | 258 259#### KCS Data Register Commands 260 261| Command | Description | 262|---------|-------------| 263| 0x00 | Initialise | 264| 0x01 | Tx Begin | 265| 0x02 | Rx Complete | 266| 0xff | Dummy Value | 267 268#### Host Command to BMC Sequence 269 270The host sends commands to the BMC to signal channel initialisation, begin 271transmission of a packet, or to complete reception of a packet. 272 273| Step | Description | 274|------|---------------------------------------------------------| 275| 1 | The host writes a command value to IDR | 276| 2 | The hardware sets IBF, which triggers a BMC interrupt | 277| 3 | The BMC reads the status register for IBF | 278| 4 | If IBF is set, the BMC reads the host command from IDR | 279| 5 | The interrupt is acknowledged by the data register read | 280 281#### BMC Command to Host Sequence 282 283The BMC sends commands to the host to begin transmission of a packet or to 284complete reception of a packet. 285 286| Step | Description | 287|------|---------------------------------------------------------| 288| 1 | The BMC writes a command value to ODR | 289| 2 | The hardware sets OBF, which triggers a host interrupt | 290| 3 | The host reads the status register for OBF | 291| 4 | If OBF is set, the host reads the BMC command from ODR | 292| 5 | The interrupt is acknowledged by the data register read | 293 294#### BMC Status Update Sequence 295 296The BMC sends status updates to the host to signal loss of function, loss of 297channel state, or the presence of a command in the KCS data register. 298 299| Step | Description | 300|------|----------------------------------------------------------------| 301| 1 | The BMC writes the status value to the status register | 302| 2 | The BMC writes the dummy command to ODR | 303| 3 | The hardware sets OBF, which triggers a host interrupt | 304| 4 | If OBF is set, the host reads the BMC command from ODR | 305| 5 | The interrupt is acknowledged by the data register read | 306| 6 | The host observes the command is the dummy command | 307| 7 | The host reads the status register to capture the state change | 308 309#### LPC Window Ownership and Synchronisation 310 311Because the LPC FW window is shared between the host and the BMC we need 312strict rules on which entity is allowed to access it at specific times. 313 314Firstly, we have rules for modification: 315 316* The control data is only written during initialisation. The control area 317 is never modified once the channel is active. 318* Only the BMC may write to the Rx buffer described in the control area 319* Only the host may write to the Tx buffer described in the control area 320 321During packet transmission, the follow sequence occurs: 322 3231. The Tx side writes the packet to its Tx buffer 3242. The Tx side sends a `Tx Begin` message, indicating that the buffer ownership 325 is transferred 3263. The Rx side now owns the buffer, and reads the message from its Rx area 3274. The Rx side sends a `Rx Complete` once done, indicating that the buffer 328 ownership is transferred back to the Tx side. 329 330### LPC Binding Operation 331 332The binding operation is not symmetric as the BMC is the only side that can 333drive the status register. Each side's initialisation sequence is outlined 334below. 335 336The sequences below contain steps where the BMC updates the channel status and 337where commands are sent between the BMC and the host. The act of updating 338status or sending a command invokes the behaviour outlined in [KCS 339Control](#kcs-control). 340 341The packet transmission sequences assume that `BMC Active` and `Channel Active` 342are set. 343 344#### BMC Initialisation Sequence 345 346| Step | Description | 347|------|------------------------------------------| 348| 1 | The BMC initialises the control area: magic value, BMC versions and buffer parameters | 349| 2 | The BMC sets the status to `BMC Active` | 350 351#### Host Initialisation Sequence 352 353| Step | v1 | v2 | Description | 354|------|----|----|------------------------------------------------| 355| 1 | ✓ | ✓ | The host waits for the `BMC Active` state | 356| 2 | ✓ | ✓ | The host populates the its version fields | 357| 3 | | ✓ | The host derives and writes to `rx_size` the packet size associated with its desired MTU | 358| 4 | ✓ | ✓ | The host sends the `Initialise` command | 359| 5 | ✓ | ✓ | The BMC observes the `Initialise` command | 360| 6 | ✓ | ✓ | The BMC calculates and writes `negotiated_ver` | 361| 7 | | ✓ | The BMC calculates the MTUs and updates neither, one or both of `rx_size` and `tx_size` | 362| 8 | ✓ | ✓ | The BMC sets the status to `Channel Active` | 363| 9 | ✓ | ✓ | The host observes that `Channel Active` is set | 364| 10 | ✓ | ✓ | The host reads the negotiated version | 365| 11 | | ✓ | The host reads both `rx_size` and `tx_size` to derive the negotiated MTUs | 366 367#### Host Packet Transmission Sequence 368 369| Step | Description | 370|------|--------------------------------------------------------------| 371| 1 | The host waits on any previous `Rx Complete` message | 372| 3 | The host writes the packet to its Tx area (BMC Rx area) | 373| 4 | The host sends the `Tx Begin` command, transferring ownership of its Tx buffer to the BMC | 374| 5 | The BMC observes the `Tx Begin` command | 375| 6 | The BMC reads the packet from the its Rx area (host Tx area) | 376| 7 | The BMC sends the `Rx Complete` command, transferring ownership of its Rx buffer to the host | 377| 8 | The host observes the `Rx Complete` command | 378 379#### BMC Packet Transmission Sequence 380 381| Step | Description | 382|------|---------------------------------------------------------------| 383| 1 | The BMC waits on any previous `Rx Complete` message | 384| 2 | The BMC writes the packet to its Tx area (host Rx area) | 385| 3 | The BMC sends the `Tx Begin` command, transferring ownership of its Tx buffer to the host | 386| 8 | The host observes the `Tx Begin` command | 387| 9 | The host reads the packet from the host Rx area (BMC Tx area) | 388| 10 | The host sends the `Rx Complete` command, transferring ownership of its Rx buffer to the BMC | 389| 15 | The BMC observes the `Rx Complete` command | 390 391## Implementation Notes 392 393On the BMC the initial prototype implementation makes use of the following 394components: 395 396* An LPC KCS device exposed by a [binding-specific kernel driver][mctp-driver] 397* The reserved memory mapped by the LPC2AHB bridge via the [aspeed-lpc-ctrl 398 driver][aspeed-lpc-ctrl] 399* The astlpc binding found in [libmctp][libmctp] 400 401[mctp-driver]: https://github.com/openbmc/linux/commit/9a3b539a175cf4fe1f8fc2997e8a91abec25c37f 402[aspeed-lpc-ctrl]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/aspeed/aspeed-lpc-ctrl.c?h=v5.7 403[libmctp]: https://github.com/openbmc/libmctp 404 405From the host side, the LPC Firmware and KCS IO cycles are driven by 406free-standing firmware. Some firmwares exploit [libmctp][libmctp] by 407implementing the driver hooks for direct access to the LPC devices. 408 409## Alternatives Considered 410 411### The KCS MCTP Binding (DSP0254) 412 413The KCS hardware (used as the full transfer channel) can be used to transfer 414arbitrarily-sized MCTP messages. However, there are much larger overheads in 415synchronisation between host and BMC for every byte transferred. 416 417### The MCTP Serial Binding (DSP0253) 418 419We could use the VUART hardware to transfer the MCTP packets according to the 420existing MCTP Serial Binding. However, the VUART device is already used for 421console data. Multiplexing both MCTP and console would be an alternative, but 422the complexity introduced would make low-level debugging both more difficult 423and less reliable. 424 425### The BT interface 426 427The BT interface allows for block-at-time transfers. However, the BT buffer 428size is only 64 bytes on the AST2500 hardware, which does not allow us to 429comply with the MCTP Base Specification (DSP0236) that requires a 64-byte 430payload size as the minimum. The 64-byte BT buffer does not allow for MCTP and 431transport headers. 432 433Additionally, we would like to develop the MCTP channel alongside the existing 434IPMI interfaces, to allow a gradual transition from IPMI to MCTP. As the BT 435channel is already used on OpenPOWER systems for IPMI transfers, we would not 436be able to support both in parallel. 437 438### Using the AST2500 LPC Mailbox 439 440This would require enabling the SuperIO interface, which allows the host to 441access the entire BMC address space, and so introduces security 442vulnerabilities. 443