1\documentclass{report} 2\usepackage{hyperref} 3\usepackage{adjustbox} 4\usepackage{placeins} 5 6% Metadata. 7\title{CPER-JSON Specification} 8\author{\parbox{\linewidth}{\centering% 9Lawrence Tang\endgraf 10Lawrence.Tang@arm.com\endgraf\medskip}} 11\date{\parbox{\linewidth}{\centering% 12Revision v0.0.1 (\today)\endgraf 13First revision released [DATE].}} 14 15% Commands. 16\newcommand*{\thead}[1]{\multicolumn{1}{|c|}{\bfseries #1}} 17\newcommand*{\jsontable}[1]{ 18 \begin{table}[!ht] 19 \label{#1} 20 \centering 21 \begin{adjustbox}{center} 22 \begin{tabular}{|l|c|p{8cm}|} 23 \hline 24 \thead{Field Name} & \thead{Type} & \thead{Description} \\ 25 \hline 26} 27\newcommand*{\jsontableend}[1]{ 28 \hline 29 \end{tabular} 30 \end{adjustbox} 31 \caption{#1} 32 \label{table:#1} 33 \end{table} 34 \FloatBarrier 35} 36 37\begin{document} 38\maketitle 39\tableofcontents 40\listoftables 41 42% Introductory section. 43\chapter{Preface} 44\section{Introduction \& Summary} 45This document lays out a structure for representing UEFI CPER records, as described in UEFI Appendix N 46\footnote{Version referenced is \href{https://uefi.org/sites/default/files/resources/UEFI_Spec_2_9_2021_03_18.pdf}{UEFI Specification 2021/03/18}.}, 47 in a human-readable JSON format, intended to be interoperable with standard CPER binary. 48\\\\ 49The C library released with this specification allows for the conversion between UEFI CPER records, an intermediate format, and the JSON structures 50defined in this document. There is also a comprehensive JSON schema\footnote{As defined by \href{https://json-schema.org/draft/2020-12/json-schema-core.html}{JSON schema Draft (2020/12)}} included within the same repository, at \texttt{specification/json}. 51 52% Specification section. 53\chapter{Main Structure Specification} 54\section{Parent Structure (Type 1): Full Log} 55\label{section:parentstructuretype1} 56This structure contains descriptions of the CPER log header, as well as the section descriptors and 57section structures themselves within arrays, representing a full CPER log. This is the structure returned by \texttt{cper\_to\_ir(FILE* cper\_file)} as JSON IR. 58 59% Parent structure (type 1) table. 60\jsontable{table:parentstructuretype1} 61header & object & A CPER header structure as defined in Section \ref{section:headerstructure}. \\ 62\hline 63sectionDescriptors & array & An array of section descriptor objects as defined in Section \ref{section:sectiondescriptorstructure}. \\ 64\hline 65sections & array & An array of section objects as defined in Chapter \ref{chapter:sectionchapter}. These sections are at the same index as their corresponding section descriptor within the \texttt{sectionDescriptors} array.\\ 66\jsontableend{Parent structure (type 1) field table.} 67 68\section{Parent Structure (Type 2): Single Section Log} 69\label{section:parentstructuretype2} 70This structure contains a single section descriptor and section, representing a single section CPER log. 71This is the structure returned by \texttt{cper\_single\_section\_to\_ir(FILE* cper\_file)} as JSON IR. 72 73% Parent structure (type 2) table. 74\jsontable{table:parentstructuretype2} 75sectionDescriptor & object & A section descriptor object as defined in Section \ref{section:sectiondescriptorstructure}. \\ 76\hline 77sections & array & A section object as defined in Chapter \ref{chapter:sectionchapter}.\\ 78\jsontableend{Parent structure (type 2) field table.} 79 80% Header structure. 81\section{Header Structure} 82\label{section:headerstructure} 83This structure describes the JSON format of the standard CPER header as defined in section N.2.1 of the 84UEFI specification. 85 86% Header structure table. 87\jsontable{table:headerstructure} 88revision & object & A CPER revision object structure as defined in Subsection \ref{subsection:revisionstructure}. \\ 89\hline 90sectionCount & int & The number of sections that are described by the CPER record.\\ 91\hline 92severity & object & An error severity structure as described in \ref{subsection:headererrorseveritystructure}.\\ 93\hline 94validationBits & object & A CPER header validation bitfield as described in Subsection \ref{subsection:headervalidbitfieldstructure}.\\ 95\hline 96recordLength & uint64 & The total length of the binary CPER record, including the header, in bytes.\\ 97\hline 98timestamp & string (\textbf{optional}) & The attached record timestamp, if the validity field is set. Formatted identically to \texttt{Date.toJson()} (ISO 8601), minus the trailing timezone letter. Timezone is local to the machine creating the record.\\ 99\hline 100timestampIsPrecise & boolean (\textbf{optional}) & If a timestamp is attached, indicates whether the provided timestamp is precise.\\ 101\hline 102platformID & string (\textbf{optional}) & If validation bit is set, uniquely identifying GUID of the platform. Platform SMBIOS UUID should be used to populate this field.\\ 103\hline 104partitionID & string (\textbf{optional}) & If validation bit is set, GUID identifying the partition on which the error occurred.\\ 105\hline 106creatorID & string & A GUID identifying the creator of the error record. May be overwritten by subsequent owners of the record.\\ 107\hline 108notificationType & object & A CPER notification type structure as described in Subsection \ref{subsection:notificationtypestructure}.\\ 109\hline 110recordID & uint64 & A unique value which, when combined with the \texttt{creatorID} field, uniquely identifies this error record on a given system.\\ 111\hline 112flags & object & A CPER header flags structure, as defined in Subsection \ref{subsection:headerflagsstructure}.\\ 113\hline 114persistenceInfo & uint64 & Produced and consumed by the creator of the error record identified by \texttt{creatorID}. Format undefined.\\ 115\jsontableend{Header structure field table.} 116 117% Header error severity. 118\subsection{Header Error Severity Structure} 119\label{subsection:headererrorseveritystructure} 120This structure describes the error severity of a single CPER record. 121\jsontable{table:headererrorseveritystructure} 122name & string & The human readable name of this error severity, if known. \\ 123\hline 124code & uint64 & The integer value of this error severity. \\ 125\jsontableend{Header error severity structure field table.} 126 127% Header validation bitfield. 128\subsection{Header Validation Bitfield Structure} 129\label{subsection:headervalidbitfieldstructure} 130This structure describes a bitfield for validating the fields of the header of a single CPER record. 131\jsontable{table:headervalidbitfieldstructure} 132platformIDValid & boolean & Whether the "platformID" field in the header structure (\ref{section:headerstructure}) is valid. \\ 133\hline 134timestampValid & boolean & Whether the "timestamp" field in the header structure (\ref{section:headerstructure}) is valid. \\ 135\hline 136partitionIDValid & boolean & Whether the "partitionID" field in the header structure (\ref{section:headerstructure}) is valid.\\ 137\jsontableend{Header validation bitfield structure field table.} 138 139% Header notification type. 140\subsection{Notification Type Structure} 141\label{subsection:notificationtypestructure} 142This structure describes the notification type of a single CPER record. 143\jsontable{table:notificationtypestructure} 144guid & string & The GUID of this notification type. Assigned GUIDs for types of CPER records are defined in UEFI Specification section N.2.1.1.\\ 145\hline 146type & string & A human readable name, if available, of the notification type for the given GUID.\\ 147\jsontableend{Notification type structure field table.} 148 149% Header flags. 150\subsection{Header Flags Structure} 151\label{subsection:headerflagsstructure} 152This structure describes the enabled flag on a given CPER record header. 153\jsontable{table:headerflagsstructure} 154name & string & A human readable name, if available, of this flag.\\ 155\hline 156value & uint64 & The integer value of this flag.\\ 157\jsontableend{Header flags structure field table.} 158 159%Section descriptor structure. 160\section{Section Descriptor Structure} 161\label{section:sectiondescriptorstructure} 162This section describes the JSON format of a single CPER record section descriptor as defined by section N.2.2 of the UEFI specification. An array of these structures is contained within the parent structure as defined in Section \ref{section:parentstructure}. 163 164%Section descriptor structure table. 165\jsontable{table:sectiondescriptorstructure} 166sectionOffset & uint64 & The offset (in bytes) of the section body this section descriptor describes from the base of the record header.\\ 167\hline 168sectionLength & uint64 & The length (in bytes) of the section body.\\ 169\hline 170revision & object & A CPER revision structure as defined in Subsection \ref{subsection:revisionstructure}.\\ 171\hline 172validationBits.fruIDValid & boolean & Whether the "fruID" field on this section descriptor contains valid data.\\ 173validationBits.fruStringValid & boolean & Whether the "fruString" field on this section descriptor contains valid data.\\ 174\hline 175flags & object & A CPER section descriptor flags structure as described in Subsection \ref{subsection:sectiondescriptorflagsstructure}.\\ 176\hline 177sectionType.data & string & GUID data for the type of section body.\\ 178sectionType.type & string & The human readable name, if possible, for the type of section body. GUIDs for types of sectoin body are defined in UEFI specification section N.2.2 Table N-5 and section N.2.4.\\ 179\hline 180fruID & string (\textbf{optional}) & If validation field set, the FRU ID of the section reporting the error.\\ 181\hline 182severity.code & uint64 & The integer value of the severity of the described section.\\ 183severity.name & string & If available, the human readable name for the severity of the described section.\\ 184\hline 185fruText & string (\textbf{optional}) & If validation field set, ASCII string identifying the FRU hardware.\\ 186\jsontableend{Section descriptor structure field table.} 187 188% Section descriptor flags. 189\subsection{Section Descriptor Flags Structure} 190\label{subsection:sectiondescriptorflagsstructure} 191This structure describes the enabled flags on a given CPER section descriptor. 192\jsontable{table:sectiondescriptorflagsstructure} 193primary & boolean & If true, indicates the section body should be associated with the error condition.\\ 194\hline 195containmentWarning & boolean & If true, the error was not contained within the processor or memory heirarchy, and may have propagated elsewhere.\\ 196\hline 197reset & boolean & If true, indicates the component has been reset and must be re-initialised or re-enabled by the operating system.\\ 198\hline 199errorThresholdExceeded & boolean & If true, indicates the operating system may choose to discontinue use of this resource.\\ 200\hline 201resourceNotAccessible & boolean & If true, the resource could not be queried for error information due to conflicts with other system software or resources. Some fields of the section will be invalid.\\ 202\hline 203latentError & boolean & If true, indicates that action has been taken to ensure error containment, but the error has not been fully corrected. System software may choose to take further action before the data is consumed.\\ 204\hline 205propagated & boolean & If true, indicates that the error has been propagated due to hardware poisoning.\\ 206\hline 207overflow & boolean & If true, overflow of data structures used to manage errors has been detected. Some error records may be lost.\\ 208\jsontableend{Section descriptor flags structure field table.} 209 210% Generic CPER structures. 211\section{Generic CPER Structures} 212This section describes generic CPER structures that are re-used throughout the specification. 213 214% Revision. 215\subsection{Revision Structure} 216\label{subsection:revisionstructure} 217This structure describes the revision of a single CPER record or sub-structure. 218\jsontable{table:revisionstructure} 219major & int & The major version number. An increase in this revision indicates the changes are not backward compatible. \\ 220\hline 221minor & int & The minor version number. Incremented on additions of new GUID types, errata fixes, or clarifications. Backwards compatible with the same major version number. \\ 222\jsontableend{CPER revision structure field table.} 223 224% Generic Error Status 225\subsection{Generic Error Status Structure} 226\label{subsection:genericerrorstatusstructure} 227This structure describes the a generic CPER error status, that can be used by any CPER section. 228\jsontable{table:genericerrorstatusstructure} 229errorType.value & uint64 & The raw value of the error type.\\ 230errorType.name & string & The human readable name, if available, of the error type.\\ 231errorType.description & string & A human readable description, if available, of the error type.\\ 232\hline 233addressSignal & boolean & Whether the error was detected on the address signals/address portion of the transaction.\\ 234\hline 235controlSignal & boolean & Whether the error was detected on the control signals/control portion of the transaction.\\ 236\hline 237dataSignal & boolean & Whether the error was detected on the data signals/data portion of the transaction.\\ 238\hline 239detectedByResponder & boolean & Whether the error was detected by the responder of the transaction.\\ 240\hline 241detectedByRequester & boolean & Whether the error was detected by the requester of the transaction.\\ 242\hline 243firstError & boolean & If multiple errors are logged for a single type of section, this indicates this is the first error in a chronological sequence. This field is optional to set.\\ 244\hline 245overflowDroppedLogs & boolean & Additional errors occurred and were not logged due to lack of resources.\\ 246\jsontableend{Generic Error Status structure field table.} 247 248%Sections. 249\chapter{Section Specification} 250\label{chapter:sectionchapter} 251This chapter defines section body formats for all of the sections defined within UEFI Specification section N.2.4. 252 253% Generic processor error section. 254\section{Generic Processor Error Section} 255\label{section:genericprocessorerrorsection} 256This section describes the JSON format for a single Generic Processor Error Section from a CPER record. The GUID used for Generic Processor Error Sections is \texttt{\{0x9876CCAD, 0x47B4, 0x4bdb, \{0xB6, 0x5E, 0x16, 0xF1, 0x93, 0xC4, 0xF3, 0xDB\}\}}. 257\jsontable{table:genericprocessorerrorsection} 258validationBits & object & A Generic Processor Error Validation Structure, as described in Subsection \ref{subsection:genericprocessorvalidationstructure}.\\ 259\hline 260processorType.name & string & If available, the human readable name of the processor type.\\ 261processorType.value & uint64 & The integer value of the processor type.\\ 262\hline 263processorISA.name & string & If available, the human readable name of the processor ISA.\\ 264processorISA.value & uint64 & The integer value corresponding to the processor ISA.\\ 265\hline 266errorType.name & string & If available, the human readable name of the type of processor error this section describes.\\ 267errorType.value & uint64 & The integer value corresponding to the processor error type.\\ 268\hline 269operation.name & string & If available, the human readable name of the operation.\\ 270operation.value & uint64 & The integer value corresponding to the operation.\\ 271\hline 272flags & object & Flag information for the Generic Processor Error as described in Subsection \ref{subsection:genericprocessorflagsstructure}.\\ 273\hline 274level & int & The level of the structure at which the error occurred.\\ 275\hline 276cpuVersionInfo & uint64 & The CPU version information as reported by CPUID with EAX=1. On ARM, this is MIDR\_EL1.\\ 277\hline 278cpuBrandString & string & The ASCII brand string of the CPU. This field is optional on ARM.\\ 279\hline 280processorID & uint64 & The unique identifier of the logical processor. On ARM, this is MPIDR\_EL1.\\ 281\hline 282targetAddress & uint64 & The target address associated with the error.\\ 283\hline 284requestorID & uint64 & ID of the requestor associated with the error.\\ 285\hline 286responderID & uint64 & ID of the responder associated with the error.\\ 287\hline 288instructionIP & uint64 & Identifies the instruction pointer at the point of error.\\ 289\jsontableend{Generic Processor Error structure field table.} 290 291% Generic processor error validation structure. 292\subsection{Generic Processor Error Validation Structure} 293\label{subsection:genericprocessorvalidationstructure} 294This structure describes the valdation bits structure of a General Processor Error CPER section. 295\jsontable{table:genericprocessorvalidationstructure} 296processorTypeValid & boolean & Whether the "processorType" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 297\hline 298processorISAValid & boolean & Whether the "processorISA" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 299\hline 300processorErrorTypeValid & boolean & Whether the "errorType" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 301\hline 302operationValid & boolean & Whether the "operation" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 303\hline 304flagsValid & boolean & Whether the "flags" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 305\hline 306levelValid & boolean & Whether the "levelValid" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 307\hline 308cpuVersionValid & boolean & Whether the "cpuVersion" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 309\hline 310cpuBrandInfoValid & boolean & Whether the "cpuBrandInfo" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 311\hline 312cpuIDValid & boolean & Whether the "cpuID" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 313\hline 314targetAddressValid & boolean & Whether the "targetAddress" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 315\hline 316requestorIDValid & boolean & Whether the "requestorID" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 317\hline 318responderIDValid & boolean & Whether the "responderID" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 319\hline 320instructionIPValid & boolean & Whether the "instructionIP" field of the Generic Processor Error section (\ref{section:genericprocessorerrorsection}) is valid.\\ 321\jsontableend{Generic Processor Error validation structure field table.} 322 323% Generic processor error flags structure. 324\subsection{Generic Processor Error Flags Structure} 325\label{subsection:genericprocessorflagsstructure} 326This structure describes the flags structure of a General Processor Error CPER section. 327\jsontable{table:genericprocessorflagsstructure} 328restartable & boolean & Whether program execution can be restarted reliably after the error.\\ 329\hline 330preciseIP & boolean & Whether the instruction IP captured is directly associated with the error.\\ 331\hline 332overflow & boolean & Whether a machine check overflow occurred (multiple errors occurred at once).\\ 333\hline 334corrected & boolean & Whether the error was corrected by hardware/firmware.\\ 335\jsontableend{Generic Processor Error flags structure field table.} 336 337% IA32/x64 error section. 338\section{IA32/x64 Processor Error Section} 339\label{section:ia32x64errorsection} 340This section describes the JSON format for a single IA32/x64 Error Section from a CPER record. The GUID used for IA32/x64 Processor Error Sections is \texttt{\{0xDC3EA0B0, 0xA144, 0x4797, \{0xB9, 0x5B, 0x53, 0xFA, 0x24, 0x2B, 0x6E, 0x1D\}\}}. 341\jsontable{table:genericprocessorerrorsection} 342validationBits & object & IA32/x64 Processor Error Validation Structure as described in Subsection \ref{subsection:ia32x64processorflagsstructure}.\\ 343\hline 344localAPICID & uint64 & The APIC ID of the processor.\\ 345\hline 346cpuidInfo & object & IA32/x64 CPUINFO Structure as defined in Subsection \ref{subsection:ia32x64cpuinfostructure}.\\ 347\hline 348processorErrorInfo & array & Array of IA32/x64 Processor Error Info Structures as described in Subsection \ref{subsection:ia32x64processorerrorinfostructure}.\\ 349\hline 350processorContextInfo & array & Array of IA32/x64 Processor Context Info Structures as described in Subsection \ref{subsection:ia32x64processorcontextinfostructure}.\\ 351\jsontableend{IA32/x64 Processor Error structure field table.} 352 353% IA32/x64 validation bitfield structure. 354\subsection{IA32/x64 Processor Error Validation Structure} 355\label{subsection:ia32x64processorflagsstructure} 356This structure describes the validation bitfield structure of an IA32/x64 Error CPER section. 357\jsontable{table:ia32x64processorflagsstructure} 358localAPICIDValid & boolean & Whether the "localAPICID" field of the IA32/x64 Error section (\ref{section:ia32x64errorsection}) is valid.\\ 359\hline 360cpuIDInfoValid & boolean & Whether the "cpuidInfo" field of the IA32/x64 Error section (\ref{section:ia32x64errorsection}) is valid.\\ 361\hline 362processorErrorInfoNum & int & The number of IA32/x64 Processor Error Info Structures (\ref{subsection:ia32x64processorerrorinfostructure}) that are included with this error section.\\ 363\hline 364processorContextInfoNum & int & The number of IA32/x64 Processor Context Info Structures (\ref{subsection:ia32x64processorcontextinfostructure}) that are included with this error section.\\ 365\jsontableend{IA32/x64 Processor Error validation structure field table.} 366 367% IA32/x64 CPUINFO structure. 368\subsection{IA32/x64 CPUINFO Structure} 369\label{subsection:ia32x64cpuinfostructure} 370This structure describes the CPUINFO structure of an IA32/x64 Error CPER section. 371\jsontable{table:ia32x64cpuinfostructure} 372eax & uint64 & Value of the EAX register resulting from a call to CPUID with EAX=1.\\ 373\hline 374ebx & uint64 & Value of the EBX register resulting from a call to CPUID with EAX=1.\\ 375\hline 376ecx & uint64 & Value of the ECX register resulting from a call to CPUID with EAX=1.\\ 377\hline 378edx & uint64 & Value of the EDX register resulting from a call to CPUID with EAX=1.\\ 379\jsontableend{IA32/x64 CPUINFO structure field table.} 380 381% IA32/x64 Processor Error Info structure. 382\subsection{IA32/x64 Processor Error Info Structure} 383\label{subsection:ia32x64processorerrorinfostructure} 384This structure describes a single IA32/x64 Processor Error Info sub-section, which is part of the larger IA32/x64 record (\ref{section:ia32x64errorsection}). 385\jsontable{table:ia32x64processorerrorinfostructure} 386type.guid & string & A GUID indicating the type of processor error defined in this structure. See \texttt{edk/Cper.h} in the library repository for the defined GUID values.\\ 387type.name & string & The human readable name, if available, of the type of processor error defined in this structure.\\ 388\hline 389validationBits & object & An IA32/x64 Processor Error Info Validation structure, as defined in Subsection \ref{subsection:ia32x64processorerrorinfovalidationstructure}.\\ 390\hline 391checkInfo & object & Check information structure for this error. One of the structures defined in Subsections \ref{subsection:ia32x64processorerrorcheckinfocachetlbstructure}, \ref{subsection:ia32x64processorerrorcheckinfobusstructure}, or \ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}. Which section is placed here is dependent on the \texttt{type} field.\\ 392\hline 393targetAddressID & uint64 & Identifies the target address associated with the error.\\ 394\hline 395requestorID & uint64 & Identifies the requestor associated with the error.\\ 396\hline 397responderID & uint64 & Identifies the responder associated with the error.\\ 398\hline 399instructionPointer & uint64 & Identifies the instruction executing when the error occurred.\\ 400\jsontableend{IA32/x64 Processor Error Info structure field table.} 401 402% IA32/x64 Processor Error Info Validation structure. 403\subsection{IA32/x64 Processor Error Info Validation Structure} 404\label{subsection:ia32x64processorerrorinfovalidationstructure} 405This structure describes a single IA32/x64 Processor Error Info structure's valid fields, as a set of boolean values. 406\jsontable{table:ia32x64processorerrorinfovalidationstructure} 407checkInfoValid & boolean & Whether the "checkInfo" field in the Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) is valid.\\ 408\hline 409targetAddressIDValid & boolean & Whether the "targetAddressID" field in the Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) is valid.\\ 410\hline 411requestorIDValid & boolean & Whether the "requestorID" field in the Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) is valid.\\ 412\hline 413responderIDValid & boolean & Whether the "responderID" field in the Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) is valid.\\ 414\hline 415instructionPointerValid & boolean & Whether the "instructionPointer" field in the Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) is valid.\\ 416\hline 417\jsontableend{IA32/x64 Processor Error Info validation structure field table.} 418 419% IA32/x64 Processor Error Check Info (Cache/TLB Error) 420\subsection{IA32/x64 Processor Error Check Info (Cache/TLB Error) Structure} 421\label{subsection:ia32x64processorerrorcheckinfocachetlbstructure} 422This structure describes check info for an IA32/x64 Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) stemming from a cache or TLB error. 423The GUIDs for cache and TLB error check info structures can be found in the library repository's \texttt{edk/Cper.h}. 424\jsontable{table:ia32x64processorerrorcheckinfocachetlbstructure} 425validationBits & object & An IA32/x64 Processor Error Check Info (Cache/TLB/Bus) Validation structure, as defined in Subsection \ref{subsection:ia32x64processorerrorcheckinfovalidationstructure}.\\ 426\hline 427transactionType.value & uint64 & The raw value of the type of cache/TLB error that occurred.\\ 428transactionType.name & string & The human readable name, if available, of the type of cache/TLB error that occurred.\\ 429\hline 430operation.value & uint64 & The raw value of the type of cache/TLB operation that caused the error.\\ 431operation.name & string & The human readable name, if available, of the type of cache/TLB operation that caused the error.\\ 432\hline 433level & uint64 & The cache/TLB level at which the error occurred.\\ 434\hline 435processorContextCorrupt & boolean & Whether the processor context might have been corrupted.\\ 436\hline 437uncorrected & boolean & Whether the error remained uncorrected.\\ 438\hline 439preciseIP & boolean & Whether the instruction pointed pushed onto the stack is directly associated with the error.\\ 440\hline 441restartableIP & boolean & Whether program execution can be restarted reliably at the instruction pointer pushed onto the stack.\\ 442\hline 443overflow & boolean & Whether an error overflow occurred (multiple errors within a short timeframe may cause this, can indicate loss of data).\\ 444\jsontableend{IA32/x64 Processor Error Check Info (Cache/TLB Error) structure field table.} 445 446% IA32/x64 Processor Error Check Info (Bus Error) 447\subsection{IA32/x64 Processor Error Check Info (Bus Error) Structure} 448\label{subsection:ia32x64processorerrorcheckinfobusstructure} 449This structure describes check info for an IA32/x64 Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) stemming from a bus error. 450The GUID for bus error check info structures can be found in the library repository's \texttt{edk/Cper.h}. 451\jsontable{table:ia32x64processorerrorcheckinfobusstructure} 452validationBits & object & An IA32/x64 Processor Error Check Info (Cache/TLB/Bus) Validation structure, as defined in Subsection \ref{subsection:ia32x64processorerrorcheckinfovalidationstructure}.\\ 453\hline 454transactionType.value & uint64 & The raw value of the type of bus error that occurred.\\ 455transactionType.name & string & The human readable name, if available, of the type of bus error that occurred.\\ 456\hline 457operation.value & uint64 & The raw value of the type of bus operation that caused the error.\\ 458operation.name & string & The human readable name, if available, of the type of bus operation that caused the error.\\ 459\hline 460level & uint64 & The bus heirarchy level at which the error occurred.\\ 461\hline 462processorContextCorrupt & boolean & Whether the processor context might have been corrupted.\\ 463\hline 464uncorrected & boolean & Whether the error remained uncorrected.\\ 465\hline 466preciseIP & boolean & Whether the instruction pointed pushed onto the stack is directly associated with the error.\\ 467\hline 468restartableIP & boolean & Whether program execution can be restarted reliably at the instruction pointer pushed onto the stack.\\ 469\hline 470overflow & boolean & Whether an error overflow occurred (multiple errors within a short timeframe may cause this, can indicate loss of data).\\ 471\hline 472participationType.value & uint64 & The raw value of the type of participation.\\ 473participationType.name & string & The human readable name, if available, of the type of participation.\\ 474\hline 475timedOut & boolean & Whether the request timed out.\\ 476\hline 477addressSpace.value & uint64 & The raw value of the address space the error was in.\\ 478addressSpace.name & string & The human readable name, if available, of the address space the error was in.\\ 479\jsontableend{IA32/x64 Processor Error Check Info (Bus Error) structure field table.} 480 481% IA32/x64 Processor Error Check Info (MS Check Error) 482\subsection{IA32/x64 Processor Error Check Info (MS Check Error) Structure} 483\label{subsection:ia32x64processorerrorcheckinfomscheckstructure} 484This structure describes check info for an IA32/x64 Processor Error Info structure (\ref{subsection:ia32x64processorerrorinfostructure}) stemming from an MS check error. 485The GUID for MS check check info structures can be found in the library repository's \texttt{edk/Cper.h}. 486\jsontable{table:ia32x64processorerrorcheckinfomscheckstructure} 487validationBits & object & An IA32/x64 Processor Error Check Info (MS Check) Validation structure, as defined in Subsection \ref{subsection:ia32x64processorerrorcheckinfomscheckvalidationstructure}.\\ 488\hline 489errorType.value & uint64 & The raw value of the type of operation that caused the error.\\ 490errorType.name & string & The human readable name, if available, of the type of operation that caused the error.\\ 491\hline 492processorContextCorrupt & boolean & Whether the processor context might have been corrupted.\\ 493\hline 494uncorrected & boolean & Whether the error remained uncorrected.\\ 495\hline 496preciseIP & boolean & Whether the instruction pointed pushed onto the stack is directly associated with the error.\\ 497\hline 498restartableIP & boolean & Whether program execution can be restarted reliably at the instruction pointer pushed onto the stack.\\ 499\hline 500overflow & boolean & Whether an error overflow occurred (multiple errors within a short timeframe may cause this, can indicate loss of data).\\ 501\jsontableend{IA32/x64 Processor Error Check Info (MS Check Error) structure field table.} 502 503% IA32/x64 Processor Error Check Info Validation structure. 504\subsection{IA32/x64 Processor Error Check Info (Cache/TLB/Bus) Validation Structure} 505\label{subsection:ia32x64processorerrorcheckinfovalidationstructure} 506This structure describes a single IA32/x64 Processor Error Check Info structure's valid fields for cache, TLB and bus errors, as a set of boolean values. 507\jsontable{table:ia32x64processorerrorcheckinfovalidationstructure} 508transactionTypeValid & boolean & Whether the "transactionType" field in a Processor Error Check Info structure is valid.\\ 509\hline 510operationValid & boolean & Whether the "operation" field in a Processor Error Check Info structure is valid.\\ 511\hline 512levelValid & boolean & Whether the "level" field in a Processor Error Check Info structure is valid.\\ 513\hline 514processorContextCorruptValid & boolean & Whether the "processorContextCorrupt" field in a Processor Error Check Info structure is valid.\\ 515\hline 516uncorrectedValid & boolean & Whether the "uncorrected" field in a Processor Error Check Info structure is valid.\\ 517\hline 518preciseIPValid & boolean & Whether the "preciseIP" field in a Processor Error Check Info structure is valid.\\ 519\hline 520restartableIPValid & boolean & Whether the "restartableIP" field in a Processor Error Check Info structure is valid.\\ 521\hline 522overflowValid & boolean & Whether the "overflow" field in a Processor Error Check Info structure is valid.\\ 523\hline 524participationTypeValid & boolean (\textbf{optional}) & Whether the "participationType" field in the Processor Error Check Info (Bus Error) structure (\ref{subsection:ia32x64processorerrorcheckinfobusstructure}) is valid. \textbf{This field is only present on bus related check info structures.}\\ 525\hline 526timedOutValid & boolean (\textbf{optional}) & Whether the "timeOut" field in the Processor Error Check Info (Bus Error) structure (\ref{subsection:ia32x64processorerrorcheckinfobusstructure}) is valid. \textbf{This field is only present on bus related check info structures.}\\ 527\hline 528addressSpaceValid & boolean (\textbf{optional}) & Whether the "addressSpace" field in the Processor Error Check Info (Bus Error) structure (\ref{subsection:ia32x64processorerrorcheckinfobusstructure}) is valid. \textbf{This field is only present on bus related check info structures.}\\ 529\jsontableend{IA32/x64 Processor Error Check Info (Cache/TLB/Bus) validation structure field table.} 530 531% IA32/x64 Processor Error Check Info (MS Check) Validation structure. 532\subsection{IA32/x64 Processor Error Check Info (MS Check) Validation Structure} 533\label{subsection:ia32x64processorerrorcheckinfomscheckvalidationstructure} 534This structure describes a single IA32/x64 Processor Error Check Info structure's valid fields for MS check errors, as a set of boolean values. 535\jsontable{table:ia32x64processorerrorcheckinfomscheckvalidationstructure} 536errorTypeValid & boolean & Whether the "transactionType" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 537\hline 538processorContextCorruptValid & boolean & Whether the "processorContextCorrupt" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 539\hline 540uncorrectedValid & boolean & Whether the "uncorrected" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 541\hline 542preciseIPValid & boolean & Whether the "preciseIP" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 543\hline 544restartableIPValid & boolean & Whether the "restartableIP" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 545\hline 546overflowValid & boolean & Whether the "overflow" field in a Processor Error Check Info (MS Check) (\ref{subsection:ia32x64processorerrorcheckinfomscheckstructure}) structure is valid.\\ 547\jsontableend{IA32/x64 Processor Error Check Info (MS Check) validation structure field table.} 548 549% IA32/x64 Processor Context Info structure. 550\subsection{IA32/x64 Processor Context Info Structure} 551\label{subsection:ia32x64processorcontextinfostructure} 552This structure describes a single IA32/x64 Processor Context Info sub-section, which is part of the larger IA32/x64 record (\ref{section:ia32x64errorsection}). 553\jsontable{table:ia32x64processorcontextinfostructure} 554registerContextType.value & uint64 & The raw value of the type of processor context state being reported.\\ 555registerContextType.name & string & The human readable name, if available, of the type of processor context state being reported.\\ 556\hline 557registerArraySize & uint64 & The total size of the array for the data type being reported, in bytes.\\ 558\hline 559msrAddress & uint64 & The starting MSR address. Valid when the \texttt{registerContextType.value} field is "1" (MSR Registers).\\ 560\hline 561mmRegisterAddress & uint64 & The starting memory address for when the \texttt{registerContextType.value} field is "7" (Memory Mapped Registers).\\ 562\hline 563registerArray & object & Register data, formatted as object fields. If the \texttt{registerContextType.value} field has the value "2" or "3", this takes the structure of Subsections \ref{subsection:ia32x64ia32registerstatestructure} and \ref{subsection:ia32x64x64registerstatestructure} respectively. If the value is any other, it takes the form of the structure defined in Subsection \ref{subsection:ia32x64unformattedregisterstatestructure}.\\ 564\jsontableend{IA32/x64 Processor Context Info structure field table.} 565 566% IA32/x64 IA32 Register State structure 567\subsection{IA32/x64 IA32 Register State Structure} 568\label{subsection:ia32x64ia32registerstatestructure} 569This structure describes a single IA32/x64 IA32 register state, which is contained in IA32/x64 Processor Context Info structures (\ref{subsection:ia32x64processorcontextinfostructure}) when \texttt{registerContextType.value} has the value "2". 570\jsontable{table:ia32x64ia32registerstatestructure} 571eax & uint64 & The EAX register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 572\hline 573ebx & uint64 & The EBX register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 574\hline 575ecx & uint64 & The ECX register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 576\hline 577edx & uint64 & The EDX register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 578\hline 579esi & uint64 & The ESI register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 580\hline 581edi & uint64 & The EDI register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 582\hline 583ebp & uint64 & The EBP register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 584\hline 585esp & uint64 & The ESP register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 586\hline 587cs & uint64 & The CS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 588\hline 589ds & uint64 & The DS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 590\hline 591ss & uint64 & The SS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 592\hline 593es & uint64 & The ES register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 594\hline 595fs & uint64 & The FS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 596\hline 597gs & uint64 & The GS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 598\hline 599eflags & uint64 & The EFLAGS register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 600\hline 601eip & uint64 & The EIP register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 602\hline 603cr0 & uint64 & The CR0 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 604\hline 605cr1 & uint64 & The CR1 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 606\hline 607cr2 & uint64 & The CR2 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 608\hline 609cr3 & uint64 & The CR3 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 610\hline 611cr4 & uint64 & The CR4 register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 612\hline 613gdtr & uint64 & The GDTR register.\\ 614\hline 615idtr & uint64 & The IDTR register.\\ 616\hline 617ldtr & uint64 & The LDTR register.\\ 618\hline 619tr & uint64 & The TR register. Real maximum is \texttt{UINT32}, null extended to \texttt{UINT64}.\\ 620\jsontableend{IA32/x64 IA32 Register State structure field table.} 621 622% IA32/x64 x64 Register State structure 623\subsection{IA32/x64 x64 Register State Structure} 624\label{subsection:ia32x64x64registerstatestructure} 625This structure describes a single IA32/x64 x64 register state, which is contained in IA32/x64 Processor Context Info structures (\ref{subsection:ia32x64processorcontextinfostructure}) when \texttt{registerContextType.value} has the value "3". 626\jsontable{table:ia32x64x64registerstatestructure} 627rax & uint64 & The RAX register.\\ 628\hline 629rbx & uint64 & The RBX register.\\ 630\hline 631rcx & uint64 & The RCX register.\\ 632\hline 633rdx & uint64 & The RDX register.\\ 634\hline 635rsi & uint64 & The RSI register.\\ 636\hline 637rdi & uint64 & The RDI register.\\ 638\hline 639rbp & uint64 & The RBP register.\\ 640\hline 641rsp & uint64 & The RSP register.\\ 642\hline 643r8 & uint64 & The R8 register.\\ 644\hline 645r9 & uint64 & The R9 register.\\ 646\hline 647r10 & uint64 & The R10 register.\\ 648\hline 649r11 & uint64 & The R11 register.\\ 650\hline 651r12 & uint64 & The R12 register.\\ 652\hline 653r13 & uint64 & The R13 register.\\ 654\hline 655r14 & uint64 & The R14 register.\\ 656\hline 657r15 & uint64 & The R15 register.\\ 658\hline 659cs & uint64 & The CS register.\\ 660\hline 661ds & uint64 & The DS register.\\ 662\hline 663ss & uint64 & The SS register.\\ 664\hline 665es & uint64 & The ES register.\\ 666\hline 667fs & uint64 & The FS register.\\ 668\hline 669gs & uint64 & The GS register.\\ 670\hline 671rflags & uint64 & The RFLAGS register.\\ 672\hline 673eip & uint64 & The EIP register.\\ 674\hline 675cr0 & uint64 & The CR0 register.\\ 676\hline 677cr1 & uint64 & The CR1 register.\\ 678\hline 679cr2 & uint64 & The CR2 register.\\ 680\hline 681cr3 & uint64 & The CR3 register.\\ 682\hline 683cr4 & uint64 & The CR4 register.\\ 684\hline 685cr8 & uint64 & The CR8 register.\\ 686\hline 687gdtr\_0 & uint64 & The first \texttt{UINT64} of the GDTR register.\\ 688\hline 689gdtr\_1 & uint64 & The second \texttt{UINT64} of the GDTR register.\\ 690\hline 691idtr\_0 & uint64 & The first \texttt{UINT64} of the IDTR register.\\ 692\hline 693idtr\_1 & uint64 & The second \texttt{UINT64} of the IDTR register.\\ 694\hline 695ldtr & uint64 & The LDTR register.\\ 696\hline 697tr & uint64 & The TR register.\\ 698\jsontableend{IA32/x64 x64 Register State structure field table.} 699 700% IA32/x64 IA32 Register State structure 701\subsection{IA32/x64 Unformatted Register State Structure} 702\label{subsection:ia32x64unformattedregisterstatestructure} 703This structure describes a single IA32/x64 unformatted register state, which is contained in IA32/x64 Processor Context Info structures (\ref{subsection:ia32x64processorcontextinfostructure}) when\\\texttt{registerContextType.value} has a value other than "2" or "3". 704\jsontable{table:ia32x64unformattedregisterstatestructure} 705data & string & A base64-formatted binary representation of the register array.\\ 706\jsontableend{IA32/x64 Unformatted Register State structure field table.} 707 708% ARM processor error section. 709\section{ARM Processor Error Section} 710\label{section:armprocessorerrorsection} 711This section describes the JSON format for a single ARM Processor Error Section from a CPER record. The GUID used for ARM Processor Error Sections is \texttt{\{ 0xe19e3d16, 0xbc11, 0x11e4, \{ 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 \}\}}. 712\jsontable{table:armprocessorerrorsection} 713validationBits & object & An ARM Processor Error Validation structure, as defined in Subsection \ref{subsection:armprocessorerrorvalidationstructure}.\\ 714\hline 715errorInfoNum & int & The number of error info structures attached to this error.\\ 716\hline 717contextInfoNum & int & The number of context info structures attached to this error.\\ 718\hline 719sectionLength & uint64 & The total size (in bytes) of this error section.\\ 720\hline 721errorAffinity.value & int & The raw value of the error affinity for this error.\\ 722errorAffinity.type & string & The human readable type of the error affinity for this error. All values are vendor defined, so specific names cannot be provided.\\ 723\hline 724mpidrEl1 & uint64 & The processor ID (\texttt{MPIDR\_EL1}) for this error.\\ 725\hline 726midrEl1 & uint64 & The chip ID (\texttt{MIDR\_EL1}) for this error.\\ 727\hline 728running & boolean & Whether the processor is running or not. If true, the \texttt{psciState} field is not included.\\ 729\hline 730psciState & uint64 (\textbf{optional}) & The PSCI state of the processor. Only \textbf{optionally} included when the "running" field is false. Cannot be made human readable, as this could either be in the pre-PSCI 1.0 format, or the newer "Extended StateID" format. For more information, see the ARM PSCI specification.\\ 731\hline 732errorInfo & array & Array of ARM Processor Error Info structures, as defined in Subsection \ref{subsection:armprocessorerrorinfostructure}.\\ 733\hline 734contextInfo & array & Array of ARM Processor Context Info structures, as defined in Subsection \ref{subsection:armprocessorcontextinfostructure}.\\ 735\hline 736vendorSpecificInfo.data & string (\textbf{optional}) & If it exists, a base64-encoded binary representation of any attached vendor specific information.\\ 737\jsontableend{ARM Processor Error structure field table.} 738 739% ARM Processor Error Validation structure 740\subsection{ARM Processor Error Validation Structure} 741\label{subsection:armprocessorerrorvalidationstructure} 742This structure describes which fields are valid in a single ARM Processor Error structure (\ref{section:armprocessorerrorsection}) with boolean fields. 743\jsontable{table:armprocessorerrorvalidationstructure} 744mpidrValid & boolean & Whether the "mpidrEl1" field in the ARM Processor Error structure (\ref{section:armprocessorerrorsection}) is valid.\\ 745\hline 746errorAffinityLevelValid & boolean & Whether the "errorAffinity" field in the ARM Processor Error structure (\ref{section:armprocessorerrorsection}) is valid.\\ 747\hline 748runningStateValid & boolean & Whether the "running" field in the ARM Processor Error structure (\ref{section:armprocessorerrorsection}) is valid.\\ 749\hline 750vendorSpecificInfoValid & boolean & Whether the trailing vendor specific info (if present) in the ARM Processor Error Structure (\ref{section:armprocessorerrorsection}) is valid.\\ 751\jsontableend{ARM Processor Error validation structure field table.} 752 753% ARM Processor Error Info structure 754\subsection{ARM Processor Error Info Structure} 755\label{subsection:armprocessorerrorinfostructure} 756This structure describes a single ARM Processor Error Info structure, as part of a whole ARM Processor Error structure (\ref{section:armprocessorerrorsection}). 757\jsontable{table:armprocessorerrorinfostructure} 758version & int & The version of the structure that is implemented.\\ 759\hline 760length & int & The length of the structure, in bytes. For version 0, this is 32.\\ 761\hline 762validationBits & object & An ARM Processor Error Info Validation structure as defined in Subsection \ref{subsection:armprocessorerrorinfovalidationstructure}.\\ 763\hline 764errorType.value & uint64 & The raw value of the error type this error info describes.\\ 765errorType.name & string & The human readable name, if available, of the error type this error info describes.\\ 766\hline 767multipleError.value & int & If the value of this field is 2 or greater, the raw value of the number of errors that occurred. Otherwise, the raw value of the multiple error status.\\ 768multipleError.type & string & The human readable value, if available, of what type of multiple error this is (single error, multiple error).\\ 769\hline 770flags & object & An ARM Processor Error Info Flags structure as defined in Subsection \ref{subsection:armprocessorerrorinfoflagsstructure}.\\ 771\hline 772errorInformation & object & An error information structure, as defined in one of Subsections \ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure} or \ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}, or . Which structure this is depends on the \texttt{errorType.value} field.\\ 773\hline 774virtualFaultAddress & uint64 & Indicates a virtual fault address associated with the error, such as when an error occurs in virtually indexed cache.\\ 775\hline 776physicalFaultAddress & uint64 & Indicates a physical fault address associated with the error.\\ 777\jsontableend{ARM Processor Error Info structure field table.} 778 779% ARM Processor Error Info Validation structure 780\subsection{ARM Processor Error Info Validation Structure} 781\label{subsection:armprocessorerrorinfovalidationstructure} 782This structure describes the valid fields in a single ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}), using boolean fields. 783\jsontable{table:armprocessorerrorinfovalidationstructure} 784multipleErrorValid & boolean & Whether the "multipleError" field in the ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}) is valid.\\ 785\hline 786flagsValid & boolean & Whether the "flags" field in the ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}) is valid.\\ 787\hline 788errorInformationValid & boolean & Whether the "errorInformation" field in the ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}) is valid.\\ 789\hline 790virtualFaultAddressValid & boolean & Whether the "virtualFaultAddress" field in the ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}) is valid.\\ 791\hline 792physicalFaultAddressValid & boolean & Whether the "physicalFaultAddress" field in the ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}) is valid.\\ 793\jsontableend{ARM Processor Error Info validation structure field table.} 794 795% ARM Processor Error Info Validation structure 796\subsection{ARM Processor Error Info Flags Structure} 797\label{subsection:armprocessorerrorinfoflagsstructure} 798This structure describes the flags in a single ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}), using boolean fields. 799\jsontable{table:armprocessorerrorinfoflagsstructure} 800firstErrorCaptured & boolean & Whether this is the first error captured.\\ 801\hline 802lastErrorCaptured & boolean & Whether this is the last error captured.\\ 803\hline 804propagated & boolean & Whether the error has propagated.\\ 805\hline 806overflow & boolean & Whether error buffer overflow was detected. This is usually from multiple errors occurring in a short timespan, and indicates loss of error data.\\ 807\jsontableend{ARM Processor Error Info Flags structure field table.} 808 809% ARM Processor Error Info Error Information (Cache/TLB) structure 810\subsection{ARM Processor Error Info Cache/TLB Information Structure} 811\label{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure} 812This structure describes cache/TLB error information for a single ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}). This structure is used when the \texttt{type} field of that structure has the value 0 or 1. 813\jsontable{table:armprocessorerrorinfoerrorinformationcachetlbstructure} 814validationBits & object & An ARM Processor Info Cache/TLB Validation structure as defined in Subsection \ref{subsection:armprocessorerrorinfocachetlbvalidationstructure}.\\ 815\hline 816transactionType.value & uint64 & The raw value of the type of cache/TLB error.\\ 817transactionType.name & string & The human readable name, if available, of the type of cache/TLB error.\\ 818\hline 819operation.value & uint64 & The raw value of the cache/TLB operation that caused the error.\\ 820operation.name & string & The human readable name, if available, of the cache/TLB operation that caused the error.\\ 821\hline 822level & int & The cache/TLB level that the error occurred at.\\ 823\hline 824processorContextCorrupt & boolean & Whether the processor context may have been corrupted.\\ 825\hline 826corrected & boolean & Whether the error was corrected.\\ 827\hline 828precisePC & boolean & Whether the program counter is directly associated with the error.\\ 829\hline 830restartablePC & boolean & Whether program execution can be restarted reliably at the program counter associated with the error.\\ 831\jsontableend{ARM Processor Error Info Cache/TLB Information structure field table.} 832 833% ARM Processor Error Info Error Information (Cache/TLB) validation structure 834\subsection{ARM Processor Error Info Cache/TLB Validation Structure} 835\label{subsection:armprocessorerrorinfocachetlbvalidationstructure} 836This structure describes valid fields in a single ARM Processor Error Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}), as a set of boolean fields. 837\jsontable{table:armprocessorerrorinfocachetlbvalidationstructure} 838transactionTypeValid & boolean & Whether the "transactionType" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 839\hline 840operationValid & boolean & Whether the "operation" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 841\hline 842levelValid & boolean & Whether the "level" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 843\hline 844processorContextCorruptValid & boolean & Whether the "processorContextCorrupt" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 845\hline 846correctedValid & boolean & Whether the "corrected" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 847\hline 848precisePCValid & boolean & Whether the "precisePC" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 849\hline 850restartablePCValid & boolean & Whether the "restartablePC" field in the ARM Processor Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationcachetlbstructure}) is valid.\\ 851\jsontableend{ARM Processor Error Info Cache/TLB validation structure field table.} 852 853% ARM Processor Error Info Error Information (Bus) structure 854\subsection{ARM Processor Error Info Bus Information Structure} 855\label{subsection:armprocessorerrorinfoerrorinformationbusstructure} 856This structure describes bus error information for a single ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}). This structure is used when the \texttt{type} field of that structure has the value 2. 857\jsontable{table:armprocessorerrorinfoerrorinformationbusstructure} 858validationBits & object & An ARM Processor Info Bus Validation structure as defined in Subsection \ref{subsection:armprocessorerrorinfobusvalidationstructure}.\\ 859\hline 860transactionType.value & uint64 & The raw value of the type of bus error.\\ 861transactionType.name & string & The human readable name, if available, of the type of bus error.\\ 862\hline 863operation.value & uint64 & The raw value of the bus operation that caused the error.\\ 864operation.name & string & The human readable name, if available, of the bus operation that caused the error.\\ 865\hline 866level & int & The affinity level that the bus error occurred at.\\ 867\hline 868processorContextCorrupt & boolean & Whether the processor context may have been corrupted.\\ 869\hline 870corrected & boolean & Whether the error was corrected.\\ 871\hline 872precisePC & boolean & Whether the program counter is directly associated with the error.\\ 873\hline 874restartablePC & boolean & Whether program execution can be restarted reliably at the program counter associated with the error.\\ 875\hline 876timedOut & boolean & Whether the request timed out.\\ 877\hline 878participationType.value & uint64 & The raw value of the type of participation that occurred in the bus error.\\ 879participationType.name & string & The human readable name, if available, of the type of participation that occurred in the bus error.\\ 880\hline 881addressSpace.value & uint64 & The raw value of the address space in which the bus error occurred.\\ 882addressSpace.name & string & The human readable name, if available, of the address space in which the bus error occurred.\\ 883\hline 884memoryAttributes & int & Memory access attributes for this bus error as described in the ARM ARM.\\ 885\hline 886accessMode.value & int & The raw value of the access mode of the bus request (secure/normal).\\ 887accessMode.name & string & The human readable name, if available, of the access mode of the bus request (secure/normal).\\ 888\jsontableend{ARM Processor Error Info Bus Information structure field table.} 889 890% ARM Processor Error Info Error Information (Bus) validation structure 891\subsection{ARM Processor Error Info Bus Validation Structure} 892\label{subsection:armprocessorerrorinfobusvalidationstructure} 893This structure describes valid fields in a single ARM Processor Error Info Cache/TLB Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}), as a set of boolean fields. 894\jsontable{table:armprocessorerrorinfobusvalidationstructure} 895transactionTypeValid & boolean & Whether the "transactionType" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 896\hline 897operationValid & boolean & Whether the "operation" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 898\hline 899levelValid & boolean & Whether the "level" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 900\hline 901processorContextCorruptValid & boolean & Whether the "processorContextCorrupt" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 902\hline 903correctedValid & boolean & Whether the "corrected" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 904\hline 905precisePCValid & boolean & Whether the "precisePC" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 906\hline 907restartablePCValid & boolean & Whether the "restartablePC" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 908\hline 909participationTypeValid & boolean & Whether the "participationType" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 910\hline 911timedOutValid & boolean & Whether the "timedOut" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 912\hline 913addressSpaceValid & boolean & Whether the "addressSpace" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 914\hline 915memoryAttributesValid & boolean & Whether the "memoryAttributes" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 916\hline 917accessModeValid & boolean & Whether the "accessMode" field in the ARM Processor Info Bus Information structure (\ref{subsection:armprocessorerrorinfoerrorinformationbusstructure}) is valid.\\ 918\jsontableend{ARM Processor Error Info Bus validation structure field table.} 919 920% ARM Processor Error Info Error Information (Microarchitecture/Undefined) structure 921\subsection{ARM Processor Error Info Microarchitecture/Undefined Information Structure} 922\label{subsection:armprocessorerrorinfoerrorinformationmicroarchundefinedstructure} 923This structure describes microarchitecture/other undefined error information for a single ARM Processor Error Info structure (\ref{subsection:armprocessorerrorinfostructure}). This structure is used when the \texttt{type} field of that structure has a value other than 0-2 (inclusive). 924\jsontable{table:armprocessorerrorinfoerrorinformationmicroarchundefinedstructure} 925data & uint64 & The unformatted data represented in the error information structure.\\ 926\jsontableend{ARM Processor Error Info Microarchitecture/Undefined Information structure field table.} 927 928% ARM Processor Context Info structure 929\subsection{ARM Processor Context Info Structure} 930\label{subsection:armprocessorcontextinfostructure} 931This structure describes a single ARM Processor Context Info structure, as part of a whole ARM Processor Error structure (\ref{section:armprocessorerrorsection}). 932\jsontable{table:armprocessorcontextinfostructure} 933version & int & The version of the structure. In the referenced UEFI specification, this is 0.\\ 934\hline 935registerContextType.value & uint64 & The raw value of the type of processor context state being reported.\\ 936registerContextType.name & string & The human readable name, if available, of the type of processor context state being reported.\\ 937\hline 938registerArraySize & uint64 & The size of the attached register array, in bytes.\\ 939\hline 940registerArray & object & The attached register array, with registers encoded as object fields. Structured as shown in one of subsections \ref{subsection:armaarch32gprstructure}, \ref{subsection:armaarch32el1contextregistersstructure}, \ref{subsection:armaarch32el2contextregistersstructure}, \ref{subsection:armaarch32secureregistersstructure}, \ref{subsection:armaarch64gprstructure}, \ref{subsection:armaarch64el1contextregistersstructure}, \ref{subsection:armaarch64el2contextregistersstructure}, \ref{subsection:armaarch64el3contextregistersstructure}, \ref{subsection:armmiscregistersstructure} or \ref{subsection:armunknownregistersstructure}. Type of structure depends on the \texttt{registerContextType.value} field.\\ 941\jsontableend{ARM Processor Context Info structure field table.} 942 943% ARM AARCH32 General Purpose Registers structure 944\subsection{ARM AARCH32 General Purpose Registers Structure} 945\label{subsection:armaarch32gprstructure} 946This structure describes the register array for AARCH32 GPRs as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 0. 947\jsontable{table:armaarch32gprstructure} 948r0 & uint64 & Register R0. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 949\hline 950r1 & uint64 & Register R1. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 951\hline 952r2 & uint64 & Register R2. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 953\hline 954r3 & uint64 & Register R3. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 955\hline 956r4 & uint64 & Register R4. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 957\hline 958r5 & uint64 & Register R5. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 959\hline 960r6 & uint64 & Register R6. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 961\hline 962r7 & uint64 & Register R7. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 963\hline 964r8 & uint64 & Register R8. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 965\hline 966r9 & uint64 & Register R9. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 967\hline 968r10 & uint64 & Register R10. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 969\hline 970r11 & uint64 & Register R11. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 971\hline 972r12 & uint64 & Register R12. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 973\hline 974r13\_sp & uint64 & Register R13 (SP). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 975\hline 976r14\_lr & uint64 & Register R14 (LR). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 977\hline 978r15\_pc & uint64 & Register R15 (PC). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 979\jsontableend{ARM AARCH32 General Purpose Registers structure field table.} 980 981% ARM AARCH32 EL1 Context Registers structure 982\subsection{ARM AARCH32 EL1 Context Registers Structure} 983\label{subsection:armaarch32el1contextregistersstructure} 984This structure describes the register array for AARCH32 EL1 context registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 1. 985\jsontable{table:armaarch32el1contextregistersstructure} 986dfar & uint64 & Register DFAR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 987\hline 988dfsr & uint64 & Register DFSR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 989\hline 990ifar & uint64 & Register IFAR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 991\hline 992isr & uint64 & Register ISR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 993\hline 994mair0 & uint64 & Register MAIR0. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 995\hline 996mair1 & uint64 & Register MAIR1. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 997\hline 998midr & uint64 & Register MIDR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 999\hline 1000mpidr & uint64 & Register MPIDR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1001\hline 1002nmrr & uint64 & Register NMRR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1003\hline 1004prrr & uint64 & Register PRRR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1005\hline 1006sctlr\_ns & uint64 & Register SCTLR (NS). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1007\hline 1008spsr & uint64 & Register SPSR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1009\hline 1010spsr\_abt & uint64 & Register SPSR (ABT). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1011\hline 1012spsr\_fiq & uint64 & Register SPSR (FIQ). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1013\hline 1014spsr\_irq & uint64 & Register SPSR (IRQ). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1015\hline 1016spsr\_svc & uint64 & Register SPSR (SVC). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1017\hline 1018spsr\_und & uint64 & Register SPSR (UND). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1019\hline 1020tpidrprw & uint64 & Register TPIDR (PRW). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1021\hline 1022tpidruro & uint64 & Register TPIDR (URO). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1023\hline 1024tpidrurw & uint64 & Register TPIDR (URW). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1025\hline 1026ttbcr & uint64 & Register TTBCR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1027\hline 1028ttbr0 & uint64 & Register TTBR0. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1029\hline 1030ttbr1 & uint64 & Register TTBR1. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1031\hline 1032dacr & uint64 & Register DACR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1033\jsontableend{ARM AARCH32 EL1 Context Registers structure field table.} 1034 1035% ARM AARCH32 EL2 Context Registers structure 1036\subsection{ARM AARCH32 EL2 Context Registers Structure} 1037\label{subsection:armaarch32el2contextregistersstructure} 1038This structure describes the register array for AARCH32 EL2 context registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 2. 1039\jsontable{table:armaarch32el2contextregistersstructure} 1040elr\_hyp & uint64 & Register ELR\_HYP. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1041\hline 1042hamair0 & uint64 & Register HAMAIR0. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1043\hline 1044hamair1 & uint64 & Register HAMAIR1. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1045\hline 1046hcr & uint64 & Register HCR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1047\hline 1048hcr2 & uint64 & Register HCR2. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1049\hline 1050hdfar & uint64 & Register HDFAR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1051\hline 1052hifar & uint64 & Register HIFAR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1053\hline 1054hpfar & uint64 & Register HPFAR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1055\hline 1056hsr & uint64 & Register HSR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1057\hline 1058htcr & uint64 & Register HTCR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1059\hline 1060htpidr & uint64 & Register HTPIDR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1061\hline 1062httbr & uint64 & Register HTTBR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1063\hline 1064spsr\_hyp & uint64 & Register SPSR (HYP). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1065\hline 1066vtcr & uint64 & Register VTCR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1067\hline 1068vttbr & uint64 & Register VTTBR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1069\hline 1070dacr32\_el2 & uint64 & Register DACR32 (EL2). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1071\hline 1072\jsontableend{ARM AARCH32 EL2 Context Registers structure field table.} 1073 1074% ARM AARCH32 Secure Registers structure 1075\subsection{ARM AARCH32 Secure Registers Structure} 1076\label{subsection:armaarch32secureregistersstructure} 1077This structure describes the register array for AARCH32 secure registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 3. 1078\jsontable{table:armaarch32secureregistersstructure} 1079sctlr\_s & uint64 & Register SCTLR\_S. \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1080\hline 1081spsr\_mon & uint64 & Register SPSR (MON). \texttt{UINT32} value null extended to \texttt{UINT64}.\\ 1082\jsontableend{ARM AARCH32 Secure Registers structure field table.} 1083 1084% ARM AARCH64 General Purpose Registers structure 1085\subsection{ARM AARCH64 General Purpose Registers Structure} 1086\label{subsection:armaarch64gprstructure} 1087This structure describes the register array for AARCH64 GPRs as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 4. 1088\jsontable{table:armaarch64gprstructure} 1089x0 & uint64 & Register X0.\\ 1090\hline 1091x1 & uint64 & Register X1.\\ 1092\hline 1093x2 & uint64 & Register X2.\\ 1094\hline 1095x3 & uint64 & Register X3.\\ 1096\hline 1097x4 & uint64 & Register X4.\\ 1098\hline 1099x5 & uint64 & Register X5.\\ 1100\hline 1101x6 & uint64 & Register X6.\\ 1102\hline 1103x7 & uint64 & Register X7.\\ 1104\hline 1105x8 & uint64 & Register X8.\\ 1106\hline 1107x9 & uint64 & Register X9.\\ 1108\hline 1109x10 & uint64 & Register X10.\\ 1110\hline 1111x11 & uint64 & Register X11.\\ 1112\hline 1113x12 & uint64 & Register X12.\\ 1114\hline 1115x13 & uint64 & Register X13.\\ 1116\hline 1117x14 & uint64 & Register X14.\\ 1118\hline 1119x15 & uint64 & Register X15.\\ 1120\hline 1121x16 & uint64 & Register X16.\\ 1122\hline 1123x17 & uint64 & Register X17.\\ 1124\hline 1125x18 & uint64 & Register X18.\\ 1126\hline 1127x19 & uint64 & Register X19.\\ 1128\hline 1129x20 & uint64 & Register X20.\\ 1130\hline 1131x21 & uint64 & Register X21.\\ 1132\hline 1133x22 & uint64 & Register X22.\\ 1134\hline 1135x23 & uint64 & Register X23.\\ 1136\hline 1137x24 & uint64 & Register X24.\\ 1138\hline 1139x25 & uint64 & Register X25.\\ 1140\hline 1141x26 & uint64 & Register X26.\\ 1142\hline 1143x27 & uint64 & Register X27.\\ 1144\hline 1145x28 & uint64 & Register X28.\\ 1146\hline 1147x29 & uint64 & Register X29.\\ 1148\hline 1149x30 & uint64 & Register X30.\\ 1150\hline 1151sp & uint64 & Register SP.\\ 1152\jsontableend{ARM AARCH64 General Purpose Registers structure field table.} 1153 1154% ARM AARCH64 EL1 Context Registers structure 1155\subsection{ARM AARCH64 EL1 Context Registers Structure} 1156\label{subsection:armaarch64el1contextregistersstructure} 1157This structure describes the register array for AARCH64 EL1 context registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 5. 1158\jsontable{table:armaarch64el1contextregistersstructure} 1159elr\_el1 & uint64 & Register ELR (EL1).\\ 1160\hline 1161esr\_el1 & uint64 & Register ESR (EL1).\\ 1162\hline 1163far\_el1 & uint64 & Register FAR (EL1).\\ 1164\hline 1165isr\_el1 & uint64 & Register ISR (EL1).\\ 1166\hline 1167mair\_el1 & uint64 & Register MAIR (EL1).\\ 1168\hline 1169midr\_el1 & uint64 & Register MIDR (EL1).\\ 1170\hline 1171mpidr\_el1 & uint64 & Register MPIDR (EL1).\\ 1172\hline 1173sctlr\_el1 & uint64 & Register SCTLR (EL1).\\ 1174\hline 1175sp\_el0 & uint64 & Register SP (EL0).\\ 1176\hline 1177sp\_el1 & uint64 & Register SP (EL1).\\ 1178\hline 1179spsr\_el1 & uint64 & Register SPSR (EL1).\\ 1180\hline 1181tcr\_el1 & uint64 & Register TCR (EL1).\\ 1182\hline 1183tpidr\_el0 & uint64 & Register TPIDR (EL0).\\ 1184\hline 1185tpidr\_el1 & uint64 & Register TPIDR (EL1).\\ 1186\hline 1187tpidrro\_el0 & uint64 & Register TPIDRRO (EL0).\\ 1188\hline 1189ttbr0\_el1 & uint64 & Register TTBR0 (EL1).\\ 1190\hline 1191ttbr1\_el1 & uint64 & Register TTBR1 (EL1).\\ 1192\jsontableend{ARM AARCH64 EL1 Context Registers structure field table.} 1193 1194% ARM AARCH64 EL2 Context Registers structure 1195\subsection{ARM AARCH64 EL2 Context Registers Structure} 1196\label{subsection:armaarch64el2contextregistersstructure} 1197This structure describes the register array for AARCH64 EL2 context registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 6. 1198\jsontable{table:armaarch64el2contextregistersstructure} 1199elr\_el2 & uint64 & Register ELR (EL2).\\ 1200\hline 1201esr\_el2 & uint64 & Register ESR (EL2).\\ 1202\hline 1203far\_el2 & uint64 & Register FAR (EL2).\\ 1204\hline 1205hacr\_el2 & uint64 & Register HACR (EL2).\\ 1206\hline 1207hcr\_el2 & uint64 & Register HCR (EL2).\\ 1208\hline 1209hpfar\_el2 & uint64 & Register HPFAR (EL2).\\ 1210\hline 1211mair\_el2 & uint64 & Register MAIR (EL2).\\ 1212\hline 1213sctlr\_el2 & uint64 & Register SCTLR (EL2).\\ 1214\hline 1215sp\_el2 & uint64 & Register SP (EL2).\\ 1216\hline 1217spsr\_el2 & uint64 & Register SPSR (EL2).\\ 1218\hline 1219tcr\_el2 & uint64 & Register TCR (EL2).\\ 1220\hline 1221tpidr\_el2 & uint64 & Register TPIDR (EL2).\\ 1222\hline 1223ttbr0\_el2 & uint64 & Register TTBR0 (EL2).\\ 1224\hline 1225vtcr\_el2 & uint64 & Register VTCR (EL2).\\ 1226\hline 1227vttbr\_el2 & uint64 & Register VTTBR (EL2).\\ 1228\jsontableend{ARM AARCH64 EL2 Context Registers structure field table.} 1229 1230% ARM AARCH64 EL3 Context Registers structure 1231\subsection{ARM AARCH64 EL3 Context Registers Structure} 1232\label{subsection:armaarch64el3contextregistersstructure} 1233This structure describes the register array for AARCH64 EL3 context registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 7. 1234\jsontable{table:armaarch64el3contextregistersstructure} 1235elr\_el3 & uint64 & Register ELR (EL3).\\ 1236\hline 1237esr\_el3 & uint64 & Register ESR (EL3).\\ 1238\hline 1239far\_el3 & uint64 & Register FAR (EL3).\\ 1240\hline 1241mair\_el3 & uint64 & Register MAIR (EL3).\\ 1242\hline 1243sctlr\_el3 & uint64 & Register SCTLR (EL3).\\ 1244\hline 1245sp\_el3 & uint64 & Register SP (EL3).\\ 1246\hline 1247spsr\_el3 & uint64 & Register SPSR (EL3).\\ 1248\hline 1249tcr\_el3 & uint64 & Register TCR (EL3).\\ 1250\hline 1251tpidr\_el3 & uint64 & Register TPIDR (EL3).\\ 1252\hline 1253ttbr0\_el3 & uint64 & Register TTBR0 (EL3).\\ 1254\jsontableend{ARM AARCH64 EL3 Context Registers structure field table.} 1255 1256% ARM AARCH64 Miscellaneous Registers structure 1257\subsection{ARM AARCH64 Miscellaneous Registers Structure} 1258\label{subsection:armmiscregistersstructure} 1259This structure describes the register array for miscellaneous ARM registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has the value 8. 1260\jsontable{table:armmiscregistersstructure} 1261mrsEncoding.op2 & uint64 & MRS Encoding OP2.\\ 1262\hline 1263mrsEncoding.crm & uint64 & MRS Encoding CRm.\\ 1264\hline 1265mrsEncoding.crn & uint64 & MRS Encoding CRn.\\ 1266\hline 1267mrsEncoding.op1 & uint64 & MRS Encoding Op1.\\ 1268\hline 1269mrsEncoding.o0 & uint64 & MRS Encoding O0.\\ 1270\hline 1271value & uint64 & Value of the single register.\\ 1272\jsontableend{ARM AARCH64 Miscellaneous Registers structure field table.} 1273 1274% ARM AARCH64 Unknown Registers structure 1275\subsection{ARM AARCH64 Unknown Registers Structure} 1276\label{subsection:armunknownregistersstructure} 1277This structure describes the register array for unknown ARM registers as part of an ARM Processor Context Info Structure (\ref{subsection:armprocessorcontextinfostructure}). This structure is included when the field \texttt{registerContextType.value} has any value other than 0-8 (inclusive). 1278\jsontable{table:armunknownregistersstructure} 1279data & string & A base64 representation of the unknown binary register array data.\\ 1280\jsontableend{ARM AARCH64 Unknown Registers structure field table.} 1281 1282% Memory error section. 1283\section{Memory Error Section} 1284\label{section:memoryerrorsection} 1285This section describes the JSON format for a single Memory Error Section from a CPER record. The GUID used for Memory Error Sections is \texttt{\{ 0xa5bc1114, 0x6f64, 0x4ede, \{ 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 \}\}}. 1286\jsontable{table:memoryerrorsection} 1287validationBits & object & A Memory Error Validation structure, as described in Subsection \ref{subsection:memoryerrorvalidationstructure}.\\ 1288\hline 1289errorStatus & object & A CPER Generic Error Status structure, as described in Subsection \ref{subsection:genericerrorstatusstructure}.\\ 1290\hline 1291bank & object & Structure as described in one of Subsection \ref{subsection:memoryerrorstandardbankaddressstructure} or Subsection \ref{subsection:memoryerroraddressgroupbankaddressstructure}. Selected structure depends on the \texttt{validationBits.bankValid} field.\\ 1292\hline 1293memoryErrorType.value & uint64 & The raw value of the memory error type.\\ 1294memoryErrorType.name & string & The human readable name, if available, of the memory error type.\\ 1295\hline 1296extended.rowBit16 & boolean & Bit 16 of the row number of the memory error location.\\ 1297extended.rowBit17 & boolean & Bit 17 of the row number of the memory error location.\\ 1298extended.chipIdentification & int & The ID of the related chip.\\ 1299\hline 1300physicalAddress & uint64 & The physical address at which the error occurred.\\ 1301\hline 1302physicalAddressMask & uint64 & Defines the valid address bits in the \texttt{physicalAddress} field.\\ 1303\hline 1304node & uint64 & Identifies the node containing the memory error, if in a multi-node system.\\ 1305\hline 1306card & uint64 & The card number of the memory error location.\\ 1307\hline 1308moduleRank & uint64 & The module or rank number of the offending memory error location.\\ 1309\hline 1310device & uint64 & The device number of the memory associated with the error.\\ 1311\hline 1312row & uint64 & The first 16 bits of the row number of the memory location.\\ 1313\hline 1314column & uint64 & The column number of the memory error location.\\ 1315\hline 1316bitPosition & uint64 & The bit position at which the error occurred.\\ 1317\hline 1318requestorID & uint64 & Hardware address of the device that initiated the errored transaction.\\ 1319\hline 1320responderID & uint64 & Hardware address of the device that responded to the transaction.\\ 1321\hline 1322targetID & uint64 & Hardware address of the intended target of the transaction.\\ 1323\hline 1324rankNumber & uint64 & The rank number of the memory error location.\\ 1325\hline 1326cardSmbiosHandle & uint64 & The SMBIOS handle for the memory card's Type 16 Memory Array Structure.\\ 1327\hline 1328moduleSmbiosHandle & uint64 & The SMBIOS handle for the memory module's Type 17 Memory Device Structure.\\ 1329\jsontableend{Memory Error structure field table.} 1330 1331% Memory error validation structure. 1332\subsection{Memory Error Validation Structure} 1333\label{subsection:memoryerrorvalidationstructure} 1334This structure describes whether fields in a single Memory Error (\ref{section:memoryerrorsection}) are valid, using boolean fields. 1335\jsontable{table:memoryerrorvalidationstructure} 1336errorStatusValid & boolean & Whether the "errorStatus" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1337\hline 1338physicalAddressValid & boolean & Whether the "physicalAddress" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1339\hline 1340physicalAddressMaskValid & boolean & Whether the "physicalAddressMask" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1341\hline 1342nodeValid & boolean & Whether the "node" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1343\hline 1344cardValid & boolean & Whether the "card" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1345\hline 1346moduleValid & boolean & Whether the "module" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1347\hline 1348bankValid & boolean & Whether the "bank.value" field of a Memory Error (\ref{section:memoryerrorsection}) is valid. When the bank is addressed by group/address, refer to \texttt{bankGroupValid} and \texttt{bankAddressValid} instead.\\ 1349\hline 1350deviceValid & boolean & Whether the "device" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1351\hline 1352rowValid & boolean & Whether the "row" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1353\hline 1354memoryPlatformTargetValid & boolean & Whether the memory platform target of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1355\hline 1356memoryErrorTypeValid & boolean & Whether the "memoryErrorType" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1357\hline 1358rankNumberValid & boolean & Whether the "rankNumber" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1359\hline 1360cardHandleValid & boolean & Whether the "cardSmbiosHandle" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1361\hline 1362moduleHandleValid & boolean & Whether the "moduleSmbiosHandle" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1363\hline 1364extendedRowBitsValid & boolean & Whether the "extended.rowBit16" and "extended.rowBit17" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1365\hline 1366bankGroupValid & boolean & Whether the "bank.group" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1367\hline 1368bankAddressValid & boolean & Whether the "bank.address" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1369\hline 1370chipIdentificationValid & boolean & Whether the "extended.chipIdentification" field of a Memory Error (\ref{section:memoryerrorsection}) is valid.\\ 1371\jsontableend{Memory Error validation structure field table.} 1372 1373% Memory error normal bank addressing structure. 1374\subsection{Memory Error Standard Bank Address Structure} 1375\label{subsection:memoryerrorstandardbankaddressstructure} 1376This structure describes a simple bank address for a Memory Error section (\ref{section:memoryerrorsection}). This structure is selected when the \texttt{bankValid} field in the corresponding Memory Error Validation Structure (\ref{subsection:memoryerrorvalidationstructure}) is set to "true". 1377\jsontable{table:memoryerrorstandardbankaddressstructure} 1378value & uint64 & The value of the bank address.\\ 1379\jsontableend{Memory Error Standard Bank Address structure field table.} 1380 1381% Memory error address/group bank addressing structure. 1382\subsection{Memory Error Address/Group Bank Address Structure} 1383\label{subsection:memoryerroraddressgroupbankaddressstructure} 1384This structure describes an address/group bank address for a Memory Error section (\ref{section:memoryerrorsection}). This structure is selected when the \texttt{bankValid} field in the corresponding Memory Error Validation Structure (\ref{subsection:memoryerrorvalidationstructure}) is set to "false". 1385\jsontable{table:memoryerroraddressgroupbankaddressstructure} 1386address & uint64 & The address of the bank.\\ 1387\hline 1388group & uint64 & The group of the bank.\\ 1389\jsontableend{Memory Error Address/Group Bank Address structure field table.} 1390 1391% Memory error 2 section. 1392\section{Memory Error 2 Section} 1393\label{section:memoryerror2section} 1394This section describes the JSON format for a single Memory Error 2 Section from a CPER record. The GUID used for Memory Error 2 Sections is \texttt{\{ 0x61EC04FC, 0x48E6, 0xD813, \{ 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 \}\}}. 1395\jsontable{table:memoryerror2section} 1396validationBits & object & A Memory Error 2 Validation structure, as described in Subsection \ref{subsection:memoryerror2validationstructure}.\\ 1397\hline 1398errorStatus & object & A CPER Generic Error Status structure, as described in Subsection \ref{subsection:genericerrorstatusstructure}.\\ 1399\hline 1400bank & object & Structure as described in one of Subsection \ref{subsection:memoryerror2standardbankaddressstructure} or Subsection \ref{subsection:memoryerror2addressgroupbankaddressstructure}. Selected structure depends on the \texttt{validationBits.bankValid} field.\\ 1401\hline 1402memoryErrorType.value & uint64 & The raw value of the memory error type.\\ 1403memoryErrorType.name & string & The human readable name, if available, of the memory error type.\\ 1404\hline 1405status.value & int & The raw value of the memory error status.\\ 1406status.state & string & The human readable value, if available, of the memory error status (corrected/uncorrected).\\ 1407\hline 1408physicalAddress & uint64 & The physical address at which the error occurred.\\ 1409\hline 1410physicalAddressMask & uint64 & Defines the valid address bits in the \texttt{physicalAddress} field.\\ 1411\hline 1412node & uint64 & Identifies the node containing the memory error, if in a multi-node system.\\ 1413\hline 1414card & uint64 & The card number of the memory error location.\\ 1415\hline 1416module & uint64 & The module of the offending memory error location.\\ 1417\hline 1418device & uint64 & The device number of the memory associated with the error.\\ 1419\hline 1420row & uint64 & The first 16 bits of the row number of the memory location.\\ 1421\hline 1422column & uint64 & The column number of the memory error location.\\ 1423\hline 1424bitPosition & uint64 & The bit position at which the error occurred.\\ 1425\hline 1426rank & uint64 & The rank number of the error location.\\ 1427\hline 1428chipID & uint64 & Chip identifier. Encoded field used to address the die in 3DS packages.\\ 1429\hline 1430requestorID & uint64 & Hardware address of the device that initiated the errored transaction.\\ 1431\hline 1432responderID & uint64 & Hardware address of the device that responded to the transaction.\\ 1433\hline 1434targetID & uint64 & Hardware address of the intended target of the transaction.\\ 1435\hline 1436cardSmbiosHandle & uint64 & The SMBIOS handle for the memory card's Type 16 Memory Array Structure.\\ 1437\hline 1438moduleSmbiosHandle & uint64 & The SMBIOS handle for the memory module's Type 17 Memory Device Structure.\\ 1439\jsontableend{Memory Error 2 structure field table.} 1440 1441% Memory error 2 validation structure. 1442\subsection{Memory Error 2 Validation Structure} 1443\label{subsection:memoryerror2validationstructure} 1444This structure describes whether fields in a single Memory Error 2 (\ref{section:memoryerror2section}) are valid, using boolean fields. 1445\jsontable{table:memoryerror2validationstructure} 1446errorStatusValid & boolean & Whether the "errorStatus" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1447\hline 1448physicalAddressValid & boolean & Whether the "physicalAddress" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1449\hline 1450physicalAddressMaskValid & boolean & Whether the "physicalAddressMask" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1451\hline 1452nodeValid & boolean & Whether the "node" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1453\hline 1454cardValid & boolean & Whether the "card" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1455\hline 1456moduleValid & boolean & Whether the "module" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1457\hline 1458bankValid & boolean & Whether the "bank.value" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid. When the bank is addressed by group/address, refer to \texttt{bankGroupValid} and \texttt{bankAddressValid} instead.\\ 1459\hline 1460deviceValid & boolean & Whether the "device" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1461\hline 1462rowValid & boolean & Whether the "row" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1463\hline 1464columnValid & boolean & Whether the "column" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1465\hline 1466rankValid & boolean & Whether the "rank" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1467\hline 1468bitPositionValid & boolean & Whether the "bitPosition" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1469\hline 1470chipIDValid & boolean & Whether the "chipID" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1471\hline 1472memoryErrorTypeValid & boolean & Whether the "memoryErrorType" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1473\hline 1474statusValid & boolean & Whether the "status" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1475\hline 1476requestorIDValid & boolean & Whether the "requestorID" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1477\hline 1478responderIDValid & boolean & Whether the "responderID" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1479\hline 1480targetIDValid & boolean & Whether the "targetID" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1481\hline 1482cardHandleValid & boolean & Whether the "cardSmbiosHandle" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1483\hline 1484moduleHandleValid & boolean & Whether the "moduleSmbiosHandle" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1485\hline 1486bankGroupValid & boolean & Whether the "bankGroup" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1487\hline 1488bankAddressValid & boolean & Whether the "bankAddress" field of a Memory Error 2 (\ref{section:memoryerror2section}) is valid.\\ 1489\jsontableend{Memory Error 2 validation structure field table.} 1490 1491% Memory error 2 normal bank addressing structure. 1492\subsection{Memory Error 2 Standard Bank Address Structure} 1493\label{subsection:memoryerror2standardbankaddressstructure} 1494This structure describes a simple bank address for a Memory Error 2 section (\ref{section:memoryerror2section}). This structure is selected when the \texttt{bankValid} field in the corresponding Memory Error 2 Validation Structure (\ref{subsection:memoryerror2validationstructure}) is set to "true". 1495\jsontable{table:memoryerror2standardbankaddressstructure} 1496value & uint64 & The value of the bank address.\\ 1497\jsontableend{Memory Error 2 Standard Bank Address structure field table.} 1498 1499% Memory error 2 address/group bank addressing structure. 1500\subsection{Memory Error 2 Address/Group Bank Address Structure} 1501\label{subsection:memoryerror2addressgroupbankaddressstructure} 1502This structure describes an address/group bank address for a Memory Error 2 section (\ref{section:memoryerror2section}). This structure is selected when the \texttt{bankValid} field in the corresponding Memory Error 2 Validation Structure (\ref{subsection:memoryerror2validationstructure}) is set to "false". 1503\jsontable{table:memoryerror2addressgroupbankaddressstructure} 1504address & uint64 & The address of the bank.\\ 1505\hline 1506group & uint64 & The group of the bank.\\ 1507\jsontableend{Memory Error 2 Address/Group Bank Address structure field table.} 1508 1509% PCIe error section. 1510\section{PCIe Error Section} 1511\label{section:pcieerrorsection} 1512This section describes the JSON format for a single PCIe Error Section from a CPER record. The GUID used for PCIe Error Sections is \texttt{\{ 0xd995e954, 0xbbc1, 0x430f, \{ 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 \}\}}. 1513\jsontable{table:pcieerrorsection} 1514validationBits & object & A PCIe Error Validation structure as defined in Subsection \ref{subsection:pcieerrorvalidationstructure}.\\ 1515\hline 1516portType.value & uint64 & The raw value of the port type for this error.\\ 1517portType.name & string & The human readable name, if available, of the port type for this error.\\ 1518\hline 1519version.major & int & The major version number for the PCIe specification supported.\\ 1520version.minor & int & The minor version number for the PCIe specification supported.\\ 1521\hline 1522commandStatus.commandRegister & uint64 & The PCI command register value.\\ 1523commandStatus.statusRegister & uint64 & The PCI status register value.\\ 1524\hline 1525deviceID & object & A PCIe Device ID structure as defined in Subsection \ref{subsection:pciedeviceidstructure}.\\ 1526\hline 1527deviceSerialNumber & uint64 & The serial number of the device.\\ 1528\hline 1529bridgeControlStatus.secondaryStatusRegister & uint64 & The bridge secondary status register. \emph{This field is valid for bridges only.}\\ 1530\hline 1531bridgeControlStatus.controlRegister & uint64 & The bridge control register. \emph{This field is valid for bridges only.}\\ 1532\hline 1533capabilityStructure.data & string & A base-64 formatted binary dump of the PCIe capability structure for this device. The structure could either be a PCIe 1.1 Capability Structure (36-byte, padded to 60 bytes) or a PCIe 2.0 Capability Structure (60-byte).\\ 1534\hline 1535% aerInfo & object & A PCIe AER Extended Capability structure, as defined in Subsection \ref{subsection:pcieaerecstructure}.\\ 1536aerInfo.data & string & A base64-formatted representation of a PCIe AER Extended Capability structure.\\ 1537\jsontableend{PCIe Error structure field table.} 1538 1539% PCIe error validation structure. 1540\subsection{PCIe Error Validation Structure} 1541\label{subsection:pcieerrorvalidationstructure} 1542This structure describes which fields within a PCIe Error section (\ref{section:pcieerrorsection}) are valid, using boolean fields. 1543\jsontable{table:pcieerrorvalidationstructure} 1544portTypeValid & boolean & Whether the "portType" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1545\hline 1546versionValid & boolean & Whether the "version" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1547\hline 1548commandStatusValid & boolean & Whether the "commandStatus" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1549\hline 1550deviceIDValid & boolean & Whether the "deviceID" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1551\hline 1552deviceSerialNumberValid & boolean & Whether the "deviceSerialNumber" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1553\hline 1554bridgeControlStatusValid & boolean & Whether the "bridgeControlStatus" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1555\hline 1556capabilityStructureStatusValid & boolean & Whether the "capabilityStructure" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1557\hline 1558aerInfoValid & boolean & Whether the "aerInfo" field within a PCIe Error section (\ref{section:pcieerrorsection}) is valid.\\ 1559\hline 1560\jsontableend{PCIe Error validation structure field table.} 1561 1562% PCIe Device ID structure. 1563\subsection{PCIe Device ID Structure} 1564\label{subsection:pciedeviceidstructure} 1565This structure describes a PCIe device ID, for use in a PCI Error section (\ref{table:pcieerrorsection}). 1566\jsontable{table:pciedeviceidstructure} 1567vendorID & uint64 & The vendor ID of the PCIe device.\\ 1568\hline 1569deviceID & uint64 & The device ID of the PCIe device.\\ 1570\hline 1571classCode & uint64 & The class code of the PCIe device.\\ 1572\hline 1573functionNumber & uint64 & The function number of the PCIe device.\\ 1574\hline 1575deviceNumber & uint64 & The device number of the PCIe device.\\ 1576\hline 1577segmentNumber & uint64 & The segment number of the PCIe device.\\ 1578\hline 1579primaryOrDeviceBusNumber & uint64 & The root port/bridge primary bus number or device bus number of the PCIe device.\\ 1580\hline 1581secondaryBusNumber & uint64 & The root port/bridge secondary bus number of the PCIe device.\\ 1582\hline 1583slotNumber & uint64 & The slot number of the PCIe device.\\ 1584\jsontableend{PCIe Device ID structure field table.} 1585 1586% % PCIe Advanced Error Reporting Extended Capability structure. 1587% \subsection{PCIe AER Extended Capability Structure} 1588% \label{subsection:pcieaerecstructure} 1589% This structure describes a PCIe Advanced Error Reporting Extended Capability structure, for use in a PCI Error section (\ref{table:pcieerrorsection}). 1590% \jsontable{table:pcieaerecstructure} 1591% capabilityID & uint64 & The capability ID for this AER structure.\\ 1592% \hline 1593% capabilityVersion & uint64 & The capability structure version for this AER structure.\\ 1594% \hline 1595% uncorrectableErrorStatusRegister & uint64 & The uncorrectable error status register value.\\ 1596% \hline 1597% uncorrectableErrorMaskRegister & uint64 & The uncorrectable error mask register value.\\ 1598% \hline 1599% uncorrectableErrorSeverityRegister & uint64 & The uncorrectable error severity register value.\\ 1600% \hline 1601% correctableErrorStatusRegister & uint64 & The correctable error status register value.\\ 1602% \hline 1603% correctableErrorMaskRegister & uint64 & The correctable error mask register value.\\ 1604% \hline 1605% aeccReg & uint64 & The AECC register value.\\ 1606% \hline 1607% headerLogRegister & string & A base64-encoded binary dump of the header log register.\\ 1608% \hline 1609% rootErrorCommand & uint64 & The root error command.\\ 1610% \hline 1611% rootErrorStatus & uint64 & The root error status.\\ 1612% \hline 1613% errorSourceIDRegister & uint64 & The error source ID register.\\ 1614% \hline 1615% correctableErrorSourceIDRegister & uint64 & The correctable error source ID register.\\ 1616% \jsontableend{PCIe AER Extended Capability structure field table.} 1617 1618% PCI/PCI-X Bus error section. 1619\section{PCI/PCI-X Bus Error Section} 1620\label{section:pcibuserrorsection} 1621This section describes the JSON format for a single PCI/PCI-X Bus Error Section from a CPER record. The GUID used for PCI/PCI-X Bus Error Sections is \texttt{\{ 0xc5753963, 0x3b84, 0x4095, \{ 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd \}\}}. 1622\jsontable{table:pcibuserrorsection} 1623validationBits & object & A PCI/PCI-X Bus Error Validation structure, as described in Subsection \ref{subsection:pcibuserrorvalidationstructure}.\\ 1624\hline 1625errorStatus & object & A CPER Generic Error Status structure, as described in Subsection \ref{subsection:genericerrorstatusstructure}.\\ 1626\hline 1627errorType.value & uint64 & The raw value of the error type for this bus error.\\ 1628errorType.name & string & The human readable name, if available, of the error type for this bus error.\\ 1629\hline 1630busID.busNumber & int & The bus number of this bus ID.\\ 1631busID.segmentNumber & int & The segment number of this bus ID.\\ 1632\hline 1633busAddress & uint64 & The memory or I/O address on the bus at the time of the error.\\ 1634\hline 1635busData & uint64 & Data on the bus at the time of the error.\\ 1636\hline 1637busCommandType & string & The type of command at the time of the error. Either "PCI" or "PCI-X".\\ 1638\hline 1639busRequestorID & uint64 & The PCI bus requestor ID for the error.\\ 1640\hline 1641busCompleterID & uint64 & The PCI bus completer ID for the error.\\ 1642\hline 1643targetID & uint64 & The PCI bus intended target ID for the error.\\ 1644\jsontableend{PCI/PCI-X Bus Error structure field table.} 1645 1646% PCI/PCI-X Bus error validation structure. 1647\subsection{PCI/PCI-X Bus Error Validation Structure} 1648\label{subsection:pcibuserrorvalidationstructure} 1649This structure describes which fields within a PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) are valid, using boolean fields. 1650\jsontable{table:pcibuserrorvalidationstructure} 1651errorStatusValid & boolean & Whether the "errorStatus" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1652\hline 1653errorTypeValid & boolean & Whether the "errorType" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1654\hline 1655busIDValid & boolean & Whether the "busID" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1656\hline 1657busAddressValid & boolean & Whether the "busAddress" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1658\hline 1659busDataValid & boolean & Whether the "busData" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1660\hline 1661commandValid & boolean & Whether the "busCommandType" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1662\hline 1663requestorIDValid & boolean & Whether the "busRequestorID" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1664\hline 1665completerIDValid & boolean & Whether the "busCompleterID" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1666\hline 1667targetIDValid & boolean & Whether the "targetID" field of the PCI/PCI-X Bus Error section (\ref{section:pcibuserrorsection}) is valid.\\ 1668\jsontableend{PCI/PCI-X Bus Error validation structure field table.} 1669 1670% PCI/PCI-X Component error section. 1671\section{PCI/PCI-X Component Error Section} 1672\label{section:pcicomponenterrorsection} 1673This section describes the JSON format for a single PCI/PCI-X Component Error Section from a CPER record. The GUID used for PCI/PCI-X Component Error Sections is \texttt{\{ 0xeb5e4685, 0xca66, 0x4769, \{ 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 \}\}}. 1674\jsontable{table:pcicomponenterrorsection} 1675validationBits & object & A PCI/PCI-X Component Error Validation structure, as defined in Subsection \ref{subsection:pcicomponenterrorvalidationstructure}.\\ 1676\hline 1677errorStatus & object & A CPER Generic Error Status structure, as described in Subsection \ref{subsection:genericerrorstatusstructure}.\\ 1678\hline 1679idInfo & object & A PCI/PCI-X Component ID structure, as defined in Subsection \ref{subsection:pcicomponentidstructure}.\\ 1680\hline 1681memoryNumber & uint64 & The number of PCI/PCI-X component memory mapped register address/data pair values are present in this structure.\\ 1682\hline 1683ioNumber & uint64 & The number of PCI/PCI-X component programmed I/O register address/data pair values are present in this structure.\\ 1684\hline 1685registerDataPairs & array & An array of PCI/PCI-X Component Register Pair structures, as defined in Subsection \ref{subsection:pcicomponentregisterpairstructure}. The length corresponds to the amounts listed in fields \texttt{memoryNumber} and \texttt{ioNumber}.\\ 1686\jsontableend{PCI/PCI-X Component Error structure field table.} 1687 1688% PCI/PCI-X Component error validation structure. 1689\subsection{PCI/PCI-X Component Error Validation Structure} 1690\label{subsection:pcicomponenterrorvalidationstructure} 1691This structure describes which fields within a PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) are valid, using boolean fields. 1692\jsontable{table:pcicomponenterrorvalidationstructure} 1693errorStatusValid & boolean & Whether the "errorStatus" field of the PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) is valid.\\ 1694\hline 1695idInfoValid & boolean & Whether the "idInfo" field of the PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) is valid.\\ 1696\hline 1697memoryNumberValid & boolean & Whether the "memoryNumber" field of the PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) is valid.\\ 1698\hline 1699ioNumberValid & boolean & Whether the "ioNumber" field of the PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) is valid.\\ 1700\hline 1701registerDataPairsValid & boolean & Whether the "registerDataPairs" field of the PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}) is valid.\\ 1702\jsontableend{PCI/PCI-X Component Error validation structure field table.} 1703 1704% PCI/PCI-X Component ID structure. 1705\subsection{PCI/PCI-X Component ID Structure} 1706\label{subsection:pcicomponentidstructure} 1707This structure describes the ID of a single PCI/PCI-X component for use in a PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}). 1708\jsontable{table:pcicomponentidstructure} 1709vendorID & uint64 & The vendor ID of this PCI/PCI-X component.\\ 1710\hline 1711deviceID & uint64 & The device ID of this PCI/PCI-X component.\\ 1712\hline 1713classCode & uint64 & The class code of this PCI/PCI-X component.\\ 1714\hline 1715functionNumber & uint64 & The function number of this PCI/PCI-X component.\\ 1716\hline 1717deviceNumber & uint64 & The device number of this PCI/PCI-X component.\\ 1718\hline 1719busNumber & uint64 & The bus number of this PCI/PCI-X component.\\ 1720\hline 1721segmentNumber & uint64 & The segment number of this PCI/PCI-X component.\\ 1722\jsontableend{PCI/PCI-X Component ID structure field table.} 1723 1724% PCI/PCI-X Component Register Pair structure. 1725\subsection{PCI/PCI-X Component Register Pair Structure} 1726\label{subsection:pcicomponentregisterpairstructure} 1727This structure describes a single pair of registers from a PCI/PCI-X component for use in a PCI/PCI-X Component Error section (\ref{section:pcicomponenterrorsection}). The actual "pairs" of address and data aren't necessarily all 16 bytes allocated long, and there is no field to indicate their length, so do not assume that the address is in the first field and the data in the second. 1728\jsontable{table:pcicomponentregisterpairstructure} 1729firstHalf & uint64 & The first 8 bytes of the 16 byte register pair structure.\\ 1730\hline 1731secondHalf & uint64 & The second 8 bytes of the 16 byte register pair structure.\\ 1732\jsontableend{PCI/PCI-X Component Register Pair structure field table.} 1733 1734% Firmware error section. 1735\section{Firmware Error Section} 1736\label{section:firmwareerrorsection} 1737This section describes the JSON format for a single Firmware Error Section from a CPER record. The GUID used for Firmware Error Sections is \texttt{\{ 0x81212a96, 0x09ed, 0x4996, \{ 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed \}\}}. 1738\jsontable{table:firmwareerrorsection} 1739errorRecordType.value & uint64 & The raw value of the type of firmware error record this is.\\ 1740errorRecordType.name & string & The human readable name, if available, of the type of firmware error record this is.\\ 1741\hline 1742revision & int & The header revision of this record. For the referenced UEFI specification, this value is 2.\\ 1743\hline 1744recordID & uint64 & Identifier for the referenced firmware error record. When the \texttt{revision} field is greater than 1 (which is expected here), this value will be null.\\ 1745\hline 1746recordIDGUID & string & GUID of the firmware error record referenced by this section. \textbf{This field is only valid when the \texttt{errorRecordType} field has a value of 2.} Otherwise, this field is ignored.\\ 1747\jsontableend{Firmware Error structure field table.} 1748 1749% Generic DMAr error section. 1750\section{Generic DMAr Error Section} 1751\label{section:dmargenericerrorsection} 1752This section describes the JSON format for a single Generic DMAr Error Section from a CPER record. The GUID used for Generic DMAr Error Sections is \texttt{\{ 0x5b51fef7, 0xc79d, 0x4434, \{ 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64 \}\}}. 1753\jsontable{table:dmargenericerrorsection} 1754requesterID & int & The device ID associated with the fault condition.\\ 1755\hline 1756segmentNumber & int & The segment number associated with the device.\\ 1757\hline 1758faultReason.value & uint64 & The raw value of the reason for the fault.\\ 1759faultReason.name & string & The human readable name, if available, of the reason for the fault.\\ 1760faultReason.description & string (\textbf{optional}) & A human readable description, if available, of the reason for the fault.\\ 1761\hline 1762accessType.value & uint64 & The raw value of the access type that caused the fault.\\ 1763accessType.name & string & The human readable name, if available, of the access type that caused the fault.\\ 1764\hline 1765addressType.value & uint64 & The raw value of the addressing type that caused the fault.\\ 1766addressType.name & string & The human readable name, if available, of the addressing type that caused the fault.\\ 1767\hline 1768architectureType.value & uint64 & The raw value of the DMAr architecture type.\\ 1769architectureType.name & string & The human readable name, if available, of the DMAr architecture type.\\ 1770\hline 1771deviceAddress & uint64 & The 64-bit device virtual address contained in the faulted DMA request.\\ 1772\jsontableend{Generic DMAr Error structure field table.} 1773 1774% VT-d DMAr error section. 1775\section{VT-d DMAr Error Section} 1776\label{section:vtddmarerrorsection} 1777This section describes the JSON format for a single VT-d DMAr Error Section from a CPER record. The GUID used for VT-d DMAr Error Sections is \texttt{\{ 0x71761d37, 0x32b2, 0x45cd, \{ 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf \}\}}. 1778\jsontable{table:vtddmarerrorsection} 1779version & int & Version register value as defined in the VT-d specification.\\ 1780\hline 1781revision & int & Revision field in VT-d specific DMA remapping reporting structure.\\ 1782\hline 1783oemID & uint64 & OEM ID field in VT-d specific DMA remapping reporting structure.\\ 1784\hline 1785capabilityRegister & uint64 & Value of VT-d capability register.\\ 1786\hline 1787extendedCapabilityRegister & uint64 & Value of VT-d extended capability register.\\ 1788\hline 1789globalCommandRegister & uint64 & Value of VT-d global command register.\\ 1790\hline 1791globalStatusRegister & uint64 & Value of VT-d global status register.\\ 1792\hline 1793faultStatusRegister & uint64 & Value of VT-d fault status register.\\ 1794\hline 1795faultRecord & object & A VT-d DMAR Fault Record structure, as defined in Subsection \ref{subsection:vtddmarfaultrecordstructure}.\\ 1796\hline 1797rootEntry & string & A base64-represented binary dump of the root entry table for the associated requester ID.\\ 1798\hline 1799contextEntry & string & A base64-represented binary dump of the context entry table for the associated requester ID.\\ 1800\hline 1801pageTableEntry\_Level6 & uint64 & The page table entry for the device virtual address in page level 6.\\ 1802\hline 1803pageTableEntry\_Level5 & uint64 & The page table entry for the device virtual address in page level 5.\\ 1804\hline 1805pageTableEntry\_Level4 & uint64 & The page table entry for the device virtual address in page level 4.\\ 1806\hline 1807pageTableEntry\_Level3 & uint64 & The page table entry for the device virtual address in page level 3.\\ 1808\hline 1809pageTableEntry\_Level2 & uint64 & The page table entry for the device virtual address in page level 2.\\ 1810\hline 1811pageTableEntry\_Level1 & uint64 & The page table entry for the device virtual address in page level 1.\\ 1812\jsontableend{VT-d DMAr Error structure field table.} 1813 1814% VT-d DMAR Fault Record structure. 1815\subsection{VT-d DMAR Fault Record Structure} 1816\label{subsection:vtddmarfaultrecordstructure} 1817This structure describes a fault record, which forms part of a single VT-d DMAr Error section (\ref{section:vtddmarerrorsection}). 1818\jsontable{table:vtddmarfaultrecordstructure} 1819faultInformation & uint64 & Fault information field as defined in the VT-d specification.\\ 1820\hline 1821sourceIdentifier & uint64 & Identifier of the source of the VT-d fault.\\ 1822\hline 1823privelegeModeRequested & boolean & Whether privelege mode was requested.\\ 1824\hline 1825executePermissionRequested & boolean & Whether execute permission was requested.\\ 1826\hline 1827pasidPresent & boolean & Whether the "pasidValue" field contains valid data.\\ 1828\hline 1829faultReason & uint64 & The reason for the VT-d fault, as defined in the VT-d specification.\\ 1830\hline 1831pasidValue & uint64 & The PASID associated with the fault.\\ 1832\hline 1833addressType & uint64 & The addressing type of the fault, as defined by the VT-d specification.\\ 1834\hline 1835type.value & uint64 & The raw value of the type of VT-d fault record.\\ 1836type.name & string & The human readable name, if available, of the type of VT-d fault record.\\ 1837\jsontableend{VT-d DMAR Fault Record structure field table.} 1838 1839% IOMMU DMAr error section. 1840\section{IOMMU DMAr Error Section} 1841\label{section:iommudmarerrorsection} 1842This section describes the JSON format for a single IOMMU DMAr Error Section from a CPER record. The GUID used for IOMMU DMAr Error Sections is \texttt{\{ 0x036f84e1, 0x7f37, 0x428c, \{ 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec \}\}}. 1843\jsontable{table:iommudmarerrorsection} 1844revision & int & The IOMMU specification revision.\\ 1845\hline 1846controlRegister & uint64 & The IOMMU control register value.\\ 1847\hline 1848statusRegister & uint64 & The IOMMU status register value.\\ 1849\hline 1850eventLogEntry & string & A base-64 binary dump of the IOMMU fault-related event log entry, as defined in the IOMMU specification.\\ 1851\hline 1852deviceTableEntry & string & A base-64 representation of the value from the device table for a given requester ID.\\ 1853\hline 1854pageTableEntry\_Level6 & uint64 & Page table entry for device virtual address in page level 6.\\ 1855\hline 1856pageTableEntry\_Level5 & uint64 & Page table entry for device virtual address in page level 5.\\ 1857\hline 1858pageTableEntry\_Level4 & uint64 & Page table entry for device virtual address in page level 4.\\ 1859\hline 1860pageTableEntry\_Level3 & uint64 & Page table entry for device virtual address in page level 3.\\ 1861\hline 1862pageTableEntry\_Level2 & uint64 & Page table entry for device virtual address in page level 2.\\ 1863\hline 1864pageTableEntry\_Level1 & uint64 & Page table entry for device virtual address in page level 1.\\ 1865\jsontableend{IOMMU DMAr Error structure field table.} 1866 1867% CCIX PER error section. 1868\section{CCIX PER Error Section} 1869\label{section:ccixpererrorsection} 1870This section describes the JSON format for a single CCIX PER Error Section from a CPER record. The GUID used for CCIX PER Error Sections is \texttt{\{ 0x91335EF6, 0xEBFB, 0x4478, \{0xA6, 0xA6, 0x88, 0xB7, 0x28, 0xCF, 0x75, 0xD7 \}\}}. 1871\jsontable{table:ccixpererrorsection} 1872length & uint64 & The length (in bytes) of the entire structure.\\ 1873\hline 1874validationBits & object & A CCIX PER Validation structure as described in Subsection \ref{subsection:ccixpervalidationstructure}.\\ 1875\hline 1876ccixSourceID & int & If the agent is an HA, SA, or RA, this indicates the CCIX Agent ID of the reporting component. Otherwise, this is the CCIX Device ID.\\ 1877\hline 1878ccixPortID & int & The CCIX Port ID that reported this error.\\ 1879\hline 1880ccixPERLog & string & A base64-represented binary dump of the CCIX PER Log structure, as defined in Section 7.3.2 of the CCIX Base Specification (Rev. 1.0).\\ 1881\jsontableend{CCIX PER Error structure field table.} 1882 1883% CCIX PER Validation structure. 1884\subsection{CCIX PER Validation Structure} 1885\label{subsection:ccixpervalidationstructure} 1886This structure describes which fields are valid in a CCIX PER Error section (\ref{section:ccixpererrorsection}) using boolean fields. 1887\jsontable{table:ccixpervalidationstructure} 1888ccixSourceIDValid & boolean & Whether the "ccixSourceID" field in the CCIX PER Error Section (\ref{section:ccixpererrorsection}) is valid.\\ 1889\hline 1890ccixPortIDValid & boolean & Whether the "ccixPortID" field in the CCIX PER Error Section (\ref{section:ccixpererrorsection}) is valid.\\ 1891\hline 1892ccixPERLogValid & boolean & Whether the "ccixPERLog" field in the CCIX PER Error Section (\ref{section:ccixpererrorsection}) is valid.\\ 1893\jsontableend{CCIX PER validation structure field table.} 1894 1895% CXL Protocol error section. 1896\section{CXL Protocol Error Section} 1897\label{section:cxlprotocolerrorsection} 1898This section describes the JSON format for a single CXL Protocol Error Section from a CPER record. The GUID used for CXL Protocol Error Sections is \texttt{\{ 0x80B9EFB4, 0x52B5, 0x4DE3, \{ 0xA7, 0x77, 0x68, 0x78, 0x4B, 0x77, 0x10, 0x48 \}\}}. 1899\jsontable{table:cxlprotocolerrorsection} 1900validationBits & object & A CXL Protocol Validation structure as defined in Subsection \ref{subsection:cxlprotocolvalidationstructure}.\\ 1901\hline 1902agentType.value & uint64 & The raw value of the detecting CXL agent type.\\ 1903agentType.name & string & The human readable name, if available, of the CXL agent type.\\ 1904\hline 1905cxlAgentAddress & object & One of the structures described in Subsection \ref{subsection:cxlprotocoldeviceagentaddressstructure} or Subsection \ref{subsection:cxlprotocolrcrbaddressstructure}. Included structure is dependent on the \texttt{agentType.value} field.\\ 1906\hline 1907deviceID & object & A CXL Device ID structure, as defined in Subsection \ref{subsection:cxlprotocoldeviceidstructure}.\\ 1908\hline 1909deviceSerial & uint64 (\textbf{optional}) & The CXL device serial number. Only included if the detecting device is a CXL device (field \texttt{agentType.value} has value 0).\\ 1910\hline 1911capabilityStructure & string (\textbf{optional}) & A base64-encoded binary dump of the CXL device's PCIe capability structure. This could either be a PCIe 1.1 Capability Structure (36-byte, padded to 60 bytes), or a PCIe 2.0 Capability Structure (60-byte). Only included if the detecting device is a CXL device (field \texttt{agentType.value} has value 0).\\ 1912\hline 1913dvsecLength & int & Length (in bytes) of the CXL DVSEC structure.\\ 1914\hline 1915errorLogLength & int & Length (in bytes) of the CXL Error Log structure.\\ 1916\hline 1917cxlDVSEC & string & A base64-encoded dump of the CXL DVSEC structure. For CXL 1.1 devices, this is a "CXL DVSEC For Flex Bus Devices" structure as defined in the CXL 1.1 specification. For CXL 1.1 host downstream ports, this is the "CXL DVSEC For Flex Bus Port" structure as defined in the CXL 1.1 specification.\\ 1918\hline 1919cxlErrorLog & string & A base64-encoded dump of the CXL error log. This field contains a copy of "CXL RAS Capability Structure", as defined in the CXL 1.1 specification.\\ 1920\jsontableend{CXL Protocol Error structure field table.} 1921 1922% CXL Protocol Validation structure. 1923\subsection{CXL Protocol Validation Structure} 1924\label{subsection:cxlprotocolvalidationstructure} 1925This structure describes which fields are valid in a CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) using boolean fields. 1926\jsontable{table:cxlprotocolvalidationstructure} 1927cxlAgentTypeValid & boolean & Whether the "cxlAgentType" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1928\hline 1929cxlAgentAddressValid & boolean & Whether the "cxlAgentAddress" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1930\hline 1931deviceIDValid & boolean & Whether the "deviceID" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1932\hline 1933deviceSerialValid & boolean & Whether the "deviceSerial" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1934\hline 1935capabiltyStructureValid & boolean & Whether the "capabilityStructure" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1936\hline 1937cxlDVSECValid & boolean & Whether the "cxlDVSEC" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1938\hline 1939cxlErrorLogValid & boolean & Whether the "cxlErrorLog" field in the CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}) is valid.\\ 1940\jsontableend{CXL Protocol validation structure field table.} 1941 1942% CXL Protocol Device Agent Address structure. 1943\subsection{CXL Protocol Device Agent Address Structure} 1944\label{subsection:cxlprotocoldeviceagentaddressstructure} 1945This structure describes the address of a single CXL device agent, for use in a CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}). Included when the \texttt{agentType.value} field has the value "0". 1946\jsontable{table:cxlprotocoldeviceagentaddressstructure} 1947functionNumber & uint64 & The function number of the CXL device.\\ 1948\hline 1949deviceNumber & uint64 & The device number of the CXL device.\\ 1950\hline 1951busNumber & uint64 & The bus number of the CXL device.\\ 1952\hline 1953segmentNumber & uint64 & The segment number of the CXL device.\\ 1954\jsontableend{CXL Protocol Device Agent Address structure field table.} 1955 1956% CXL Protocol RCRB Base Address structure. 1957\subsection{CXL Protocol RCRB Base Address Structure} 1958\label{subsection:cxlprotocolrcrbaddressstructure} 1959This structure describes an RCRB base address, for use in a CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}). Included when the \texttt{agentType.value} field has the value "1". 1960\jsontable{table:cxlprotocolrcrbaddressstructure} 1961value & uint64 & The CXL port RCRB base address.\\ 1962\jsontableend{CXL Protocol RCRB Base Address structure field table.} 1963 1964% CXL Protocol Device ID structure. 1965\subsection{CXL Protocol Device ID Structure} 1966\label{subsection:cxlprotocoldeviceidstructure} 1967This structure describes the ID of a CXL device, for use in a CXL Protocol Error section (\ref{section:cxlprotocolerrorsection}). 1968\jsontable{table:cxlprotocoldeviceidstructure} 1969vendorID & uint64 & The vendor ID of the CXL device.\\ 1970\hline 1971deviceID & uint64 & The device ID of the CXL device.\\ 1972\hline 1973subsystemVendorID & uint64 & The subsystem vendor ID of the CXL device.\\ 1974\hline 1975subsystemDeviceID & uint64 & The subsystem device ID of the CXL device.\\ 1976\hline 1977classCode & uint64 & The class code of the CXL device.\\ 1978\hline 1979slotNumber & uint64 & The slot number of the CXL device.\\ 1980\jsontableend{CXL Protocol Device ID structure field table.} 1981 1982% CXL Component error section. 1983\section{CXL Component Error Section} 1984\label{section:cxlcomponenterrorsection} 1985This section describes the JSON format for a single CXL Component Error Section from a CPER record. There are several GUIDs used for CXL Component Error Sections, of which defined are:\\ 1986\begin{itemize} 1987 \item CXL General Media Error (\texttt{\{ 0xfbcd0a77, 0xc260, 0x417f, \{ 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6 \}\}})\\ 1988 \item CXL DRAM Event Error (\texttt{\{ 0x601dcbb3, 0x9c06, 0x4eab, \{ 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24 \}\}})\\ 1989 \item CXL Memory Module Error (\texttt{\{ 0xfe927475, 0xdd59, 0x4339, \{ 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74 \}\}})\\ 1990 \item CXL Physical Switch Error (\texttt{\{ 0x77cf9271, 0x9c02, 0x470b, \{ 0x9f, 0xe4, 0xbc, 0x7b, 0x75, 0xf2, 0xda, 0x97 \}\}})\\ 1991 \item CXL Virtual Switch Error (\texttt{\{ 0x40d26425, 0x3396, 0x4c4d, \{ 0xa5, 0xda, 0x3d, 0x47, 0x26, 0x3a, 0xf4, 0x25 \}\}})\\ 1992 \item CXL MLD Port Error (\texttt{\{ 0x8dc44363, 0x0c96, 0x4710, \{ 0xb7, 0xbf, 0x04, 0xbb, 0x99, 0x53, 0x4c, 0x3f \}\}})\\ 1993\end{itemize} 1994\jsontable{table:cxlcomponenterrorsection} 1995length & uint64 & The length in bytes for the entire structure.\\ 1996\hline 1997validationBits & object & A CXL Component Validation structure as described in Subsection \ref{subsection:cxlcomponentvalidationstructure}.\\ 1998\hline 1999deviceID & object & A CXL Component Device ID structure as described in Subsection \ref{subsection:cxlcomponentdeviceidstructure}.\\ 2000\hline 2001deviceSerial & uint64 & The serial of the CXL component.\\ 2002\hline 2003cxlComponentEventLog.data & string (\textbf{optional}) & If a CXL component event log is attached (\texttt{validationBits.cxlComponentEventLogValid} is true), this is a base64-represented binary dump of the CXL Component Event Log as described within CXL Specification Section 8.2.9.1.\\ 2004\jsontableend{CXL Component Error structure field table.} 2005 2006% CXL Component Validation structure. 2007\subsection{CXL Component Validation Structure} 2008\label{subsection:cxlcomponentvalidationstructure} 2009This structure describes which fields are valid in a CXL Component Error section (\ref{section:cxlcomponenterrorsection}) using boolean fields. 2010\jsontable{table:cxlcomponentvalidationstructure} 2011deviceIDValid & boolean & Whether the "deviceID" field of the CXL Component Error section (\ref{section:cxlcomponenterrorsection}) is valid.\\ 2012\hline 2013deviceSerialValid & boolean & Whether the "deviceSerial" field of the CXL Component Error section (\ref{section:cxlcomponenterrorsection}) is valid.\\ 2014\hline 2015cxlComponentEventLogValid & boolean & Whether the "cxlComponentEventLog" field of the CXL Component Error section (\ref{section:cxlcomponenterrorsection}) is valid.\\ 2016\jsontableend{CXL Component validation structure field table.} 2017 2018% CXL Component Device ID structure. 2019\subsection{CXL Component Device ID Structure} 2020\label{subsection:cxlcomponentdeviceidstructure} 2021This structure describes the ID of a CXL component, for use in a CXL Component Error section (\ref{section:cxlcomponenterrorsection}). 2022\jsontable{table:cxlcomponentdeviceidstructure} 2023vendorID & uint64 & The vendor ID of the CXL component.\\ 2024\hline 2025deviceID & uint64 & The device ID of the CXL component.\\ 2026\hline 2027functionNumber & uint64 & The function number of the CXL component.\\ 2028\hline 2029deviceNumber & uint64 & The device number of the CXL component.\\ 2030\hline 2031busNumber & uint64 & The bus of the CXL component.\\ 2032\hline 2033segmentNumber & uint64 & The segment of the CXL component.\\ 2034\hline 2035slotNumber & uint64 & The slot number of the CXL component.\\ 2036\jsontableend{CXL Component Device ID structure field table.} 2037 2038% Undefined error section. 2039\section{Undefined Error Section} 2040\label{section:undefinederrorsection} 2041This section describes the JSON format for a single undefined CPER section. This structure is used for all CPER sections that have \texttt{errorType} GUIDs which are not defined in UEFI Appendix N. 2042\jsontable{table:ccixpererrorsection} 2043data & string & A base64-encoded binary dump of the undefined CPER section.\\ 2044\jsontableend{Undefined Error structure field table.} 2045 2046\end{document}