1 #ifndef CPER_SECTION_PCIE_H
2 #define CPER_SECTION_PCIE_H
3 
4 #include "json.h"
5 #include "../edk/Cper.h"
6 
7 #define PCIE_ERROR_VALID_BITFIELD_NAMES (const char*[]) {"portTypeValid", "versionValid", "commandStatusValid", \
8     "deviceIDValid", "deviceSerialNumberValid", "bridgeControlStatusValid", "capabilityStructureStatusValid", \
9     "aerInfoValid"}
10 #define PCIE_ERROR_PORT_TYPES_KEYS (int []){0, 1, 4, 5, 6, 7, 8, 9, 10}
11 #define PCIE_ERROR_PORT_TYPES_VALUES (const char*[]){"PCI Express End Point", "Legacy PCI End Point Device", \
12     "Root Port", "Upstream Switch Port", "Downstream Switch Port", "PCI Express to PCI/PCI-X Bridge", \
13     "PCI/PCI-X Bridge to PCI Express Bridge", "Root Complex Integrated Endpoint Device", "Root Complex Event Collector"}
14 
15 typedef struct {
16     UINT64 PcieExtendedCapabilityId : 16;
17     UINT64 CapabilityVersion : 4;
18     UINT64 NextCapabilityOffset : 12;
19 } EFI_PCIE_ADV_ERROR_EXT_CAPABILITY_HEADER;
20 
21 typedef struct {
22     EFI_PCIE_ADV_ERROR_EXT_CAPABILITY_HEADER Header;
23     UINT32 UncorrectableErrorStatusReg;
24     UINT32 UncorrectableErrorMaskReg;
25     UINT32 UncorrectableErrorSeverityReg;
26     UINT32 CorrectableErrorStatusReg;
27     UINT32 CorrectableErrorMaskReg;
28     UINT32 AeccReg;
29     UINT8 HeaderLogReg[16];
30     UINT32 RootErrorCommand;
31     UINT32 RootErrorStatus;
32     UINT16 CorrectableSourceIdReg;
33     UINT16 ErrorSourceIdReg;
34 } EFI_PCIE_ADV_ERROR_EXT_CAPABILITY;
35 
36 json_object* cper_section_pcie_to_ir(void* section, EFI_ERROR_SECTION_DESCRIPTOR* descriptor);
37 
38 #endif