14dbe3d72SLawrence Tang #ifndef CPER_SECTION_PCIE_H 24dbe3d72SLawrence Tang #define CPER_SECTION_PCIE_H 34dbe3d72SLawrence Tang 45202bbb4SLawrence Tang #include <json.h> 54dbe3d72SLawrence Tang #include "../edk/Cper.h" 64dbe3d72SLawrence Tang 7*f8fc7052SJohn Chung #define PCIE_ERROR_VALID_BITFIELD_NAMES \ 8*f8fc7052SJohn Chung (const char *[]) \ 9*f8fc7052SJohn Chung { \ 10*f8fc7052SJohn Chung "portTypeValid", "versionValid", "commandStatusValid", \ 11*f8fc7052SJohn Chung "deviceIDValid", "deviceSerialNumberValid", \ 12*f8fc7052SJohn Chung "bridgeControlStatusValid", \ 13*f8fc7052SJohn Chung "capabilityStructureStatusValid", "aerInfoValid" \ 14*f8fc7052SJohn Chung } 15*f8fc7052SJohn Chung #define PCIE_ERROR_PORT_TYPES_KEYS \ 16*f8fc7052SJohn Chung (int[]) \ 17*f8fc7052SJohn Chung { \ 18*f8fc7052SJohn Chung 0, 1, 4, 5, 6, 7, 8, 9, 10 \ 19*f8fc7052SJohn Chung } 20*f8fc7052SJohn Chung #define PCIE_ERROR_PORT_TYPES_VALUES \ 21*f8fc7052SJohn Chung (const char *[]) \ 22*f8fc7052SJohn Chung { \ 23*f8fc7052SJohn Chung "PCI Express End Point", "Legacy PCI End Point Device", \ 24*f8fc7052SJohn Chung "Root Port", "Upstream Switch Port", \ 25*f8fc7052SJohn Chung "Downstream Switch Port", \ 26*f8fc7052SJohn Chung "PCI Express to PCI/PCI-X Bridge", \ 27*f8fc7052SJohn Chung "PCI/PCI-X Bridge to PCI Express Bridge", \ 28*f8fc7052SJohn Chung "Root Complex Integrated Endpoint Device", \ 29*f8fc7052SJohn Chung "Root Complex Event Collector" \ 30*f8fc7052SJohn Chung } 314dbe3d72SLawrence Tang 32*f8fc7052SJohn Chung json_object *cper_section_pcie_to_ir(void *section); 333b7f45b5SLawrence Tang void ir_section_pcie_to_cper(json_object *section, FILE *out); 344dbe3d72SLawrence Tang 354dbe3d72SLawrence Tang #endif 36