14dbe3d72SLawrence Tang #ifndef CPER_SECTION_PCIE_H 24dbe3d72SLawrence Tang #define CPER_SECTION_PCIE_H 34dbe3d72SLawrence Tang 4*255bd81aSKarthik Rajagopalan #ifdef __cplusplus 5*255bd81aSKarthik Rajagopalan extern "C" { 6*255bd81aSKarthik Rajagopalan #endif 7*255bd81aSKarthik Rajagopalan 85202bbb4SLawrence Tang #include <json.h> 94dbe3d72SLawrence Tang #include "../edk/Cper.h" 104dbe3d72SLawrence Tang 11f8fc7052SJohn Chung #define PCIE_ERROR_VALID_BITFIELD_NAMES \ 12f8fc7052SJohn Chung (const char *[]) \ 13f8fc7052SJohn Chung { \ 14f8fc7052SJohn Chung "portTypeValid", "versionValid", "commandStatusValid", \ 15f8fc7052SJohn Chung "deviceIDValid", "deviceSerialNumberValid", \ 16f8fc7052SJohn Chung "bridgeControlStatusValid", \ 17f8fc7052SJohn Chung "capabilityStructureStatusValid", "aerInfoValid" \ 18f8fc7052SJohn Chung } 19f8fc7052SJohn Chung #define PCIE_ERROR_PORT_TYPES_KEYS \ 20f8fc7052SJohn Chung (int[]) \ 21f8fc7052SJohn Chung { \ 22f8fc7052SJohn Chung 0, 1, 4, 5, 6, 7, 8, 9, 10 \ 23f8fc7052SJohn Chung } 24f8fc7052SJohn Chung #define PCIE_ERROR_PORT_TYPES_VALUES \ 25f8fc7052SJohn Chung (const char *[]) \ 26f8fc7052SJohn Chung { \ 27f8fc7052SJohn Chung "PCI Express End Point", "Legacy PCI End Point Device", \ 28f8fc7052SJohn Chung "Root Port", "Upstream Switch Port", \ 29f8fc7052SJohn Chung "Downstream Switch Port", \ 30f8fc7052SJohn Chung "PCI Express to PCI/PCI-X Bridge", \ 31f8fc7052SJohn Chung "PCI/PCI-X Bridge to PCI Express Bridge", \ 32f8fc7052SJohn Chung "Root Complex Integrated Endpoint Device", \ 33f8fc7052SJohn Chung "Root Complex Event Collector" \ 34f8fc7052SJohn Chung } 354dbe3d72SLawrence Tang 36f8fc7052SJohn Chung json_object *cper_section_pcie_to_ir(void *section); 373b7f45b5SLawrence Tang void ir_section_pcie_to_cper(json_object *section, FILE *out); 384dbe3d72SLawrence Tang 39*255bd81aSKarthik Rajagopalan #ifdef __cplusplus 40*255bd81aSKarthik Rajagopalan } 41*255bd81aSKarthik Rajagopalan #endif 42*255bd81aSKarthik Rajagopalan 434dbe3d72SLawrence Tang #endif 44