1 #ifndef CPER_SECTION_ARM_H
2 #define CPER_SECTION_ARM_H
3 
4 #include "json.h"
5 #include "../edk/Cper.h"
6 
7 #define ARM_ERROR_VALID_BITFIELD_NAMES (const char*[]) \
8     {"mpidrValid", "errorAffinityLevelValid", "runningStateValid", "vendorSpecificInfoValid"}
9 #define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES (const char*[]) \
10     {"multipleErrorValid", "flagsValid", "errorInformationValid", "virtualFaultAddressValid", "physicalFaultAddressValid"}
11 #define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES (const char*[]) \
12     {"firstErrorCaptured", "lastErrorCaptured", "propagated", "overflow"}
13 #define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES (const char*[]) \
14     {"transactionTypeValid", "operationValid", "levelValid", "processorContextCorruptValid", "correctedValid", \
15     "precisePCValid", "restartablePCValid"}
16 #define ARM_BUS_ERROR_VALID_BITFIELD_NAMES (const char*[]) \
17     {"transactionTypeValid", "operationValid", "levelValid", "processorContextCorruptValid", "correctedValid", \
18     "precisePCValid", "restartablePCValid", "participationTypeValid", "timedOutValid", "addressSpaceValid", \
19     "memoryAttributesValid", "accessModeValid"}
20 #define ARM_ERROR_TRANSACTION_TYPES_KEYS (int []){0, 1, 2}
21 #define ARM_ERROR_TRANSACTION_TYPES_VALUES (const char*[]){"Instruction", "Data Access", "Generic"}
22 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS (int []){0, 1, 2, 3}
23 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES (const char*[]){"Cache Error", "TLB Error", \
24     "Bus Error", "Micro-Architectural Error"}
25 #define ARM_CACHE_BUS_OPERATION_TYPES_KEYS (int []){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}
26 #define ARM_CACHE_BUS_OPERATION_TYPES_VALUES (const char*[]){"Generic Error", "Generic Read", "Generic Write", \
27     "Data Read", "Data Write", "Instruction Fetch", "Prefetch", "Eviction", "Snooping", "Snooped", "Management"}
28 #define ARM_TLB_OPERATION_TYPES_KEYS (int []){0, 1, 2, 3, 4, 5, 6, 7, 8}
29 #define ARM_TLB_OPERATION_TYPES_VALUES (const char*[]){"Generic Error", "Generic Read", "Generic Write", \
30     "Data Read", "Data Write", "Instruction Fetch", "Prefetch", "Local Management Operation", \
31     "External Management Operation"}
32 #define ARM_BUS_PARTICIPATION_TYPES_KEYS (int []){0, 1, 2, 3}
33 #define ARM_BUS_PARTICIPATION_TYPES_VALUES (const char*[]){"Local Processor Originated Request", \
34     "Local Processor Responded to Request", "Local Processor Observed", "Generic"}
35 #define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS (int []){0, 1, 3}
36 #define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES (const char*[]){"External Memory Access", "Internal Memory Access", \
37     "Device Memory Access"}
38 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS (int []){0, 1, 2, 3, 4, 5, 6, 7, 8}
39 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES (const char*[]){"AArch32 General Purpose Registers", \
40     "AArch32 EL1 Context Registers", "AArch32 EL2 Context Registers", "AArch32 Secure Context Registers", \
41     "AArch64 General Purpose Registers", "AArch64 EL1 Context Registers", "AArch64 EL2 Context Registers", \
42     "AArch64 EL3 Context Registers", "Miscellaneous System Register Structure"}
43 #define ARM_AARCH32_GPR_NAMES (const char*[]){"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
44     "r10", "r11", "r12", "r13_sp", "r14_lr", "r15_pc"}
45 #define ARM_AARCH32_EL1_REGISTER_NAMES (const char*[]){"dfar", "dfsr", "ifar", "isr", "mair0", "mair1", "midr", \
46     "mpidr", "nmrr", "prrr", "sctlr_ns", "spsr", "spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", \
47     "tpidrprw", "tpidruro", "tpidrurw", "ttbcr", "ttbr0", "ttbr1", "dacr"}
48 #define ARM_AARCH32_EL2_REGISTER_NAMES (const char*[]){"elr_hyp", "hamair0", "hamair1", "hcr", "hcr2", "hdfar", \
49     "hifar", "hpfar", "hsr", "htcr", "htpidr", "httbr", "spsr_hyp", "vtcr", "vttbr", "dacr32_el2"}
50 #define ARM_AARCH32_SECURE_REGISTER_NAMES (const char*[]){"sctlr_s", "spsr_mon"}
51 #define ARM_AARCH64_GPR_NAMES (const char*[]){"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", \
52     "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", \
53     "x27", "x28", "x29", "x30", "sp"}
54 #define ARM_AARCH64_EL1_REGISTER_NAMES (const char*[]){"elr_el1", "esr_el1", "far_el1", "isr_el1", "mair_el1", \
55     "midr_el1", "mpidr_el1", "sctlr_el1", "sp_el0", "sp_el1", "spsr_el1", "tcr_el1", "tpidr_el0", "tpidr_el1", \
56     "tpidrro_el0", "ttbr0_el1", "ttbr1_el1"}
57 #define ARM_AARCH64_EL2_REGISTER_NAMES (const char*[]){"elr_el2", "esr_el2", "far_el2", "hacr_el2", "hcr_el2", \
58     "hpfar_el2", "mair_el2", "sctlr_el2", "sp_el2", "spsr_el2", "tcr_el2", "tpidr_el2", "ttbr0_el2", "vtcr_el2", \
59     "vttbr_el2"}
60 #define ARM_AARCH64_EL3_REGISTER_NAMES (const char*[]){"elr_el3", "esr_el3", "far_el3", "mair_el3", "sctlr_el3", \
61     "sp_el3", "spsr_el3", "tcr_el3", "tpidr_el3", "ttbr0_el3"}
62 
63 ///
64 /// ARM Processor Error Record
65 ///
66 typedef struct {
67   UINT32    ValidFields;
68   UINT16    ErrInfoNum;
69   UINT16    ContextInfoNum;
70   UINT32    SectionLength;
71   UINT32  ErrorAffinityLevel;
72   UINT64  MPIDR_EL1;
73   UINT64  MIDR_EL1;
74   UINT32 RunningState;
75   UINT32 PsciState;
76 } EFI_ARM_ERROR_RECORD;
77 
78 ///
79 /// ARM Processor Error Information Structure
80 ///
81 #define ARM_ERROR_INFORMATION_TYPE_CACHE 0
82 #define ARM_ERROR_INFORMATION_TYPE_TLB 1
83 #define ARM_ERROR_INFORMATION_TYPE_BUS 2
84 #define ARM_ERROR_INFORMATION_TYPE_MICROARCH 3
85 
86 typedef struct {
87   UINT64 ValidationBits : 16;
88   UINT64 TransactionType : 2;
89   UINT64 Operation : 4;
90   UINT64 Level : 3;
91   UINT64 ProcessorContextCorrupt : 1;
92   UINT64 Corrected : 1;
93   UINT64 PrecisePC : 1;
94   UINT64 RestartablePC : 1;
95   UINT64 Reserved : 34;
96 } EFI_ARM_CACHE_ERROR_STRUCTURE;
97 
98 typedef struct {
99   UINT64 ValidationBits : 16;
100   UINT64 TransactionType : 2;
101   UINT64 Operation : 4;
102   UINT64 Level : 3;
103   UINT64 ProcessorContextCorrupt : 1;
104   UINT64 Corrected : 1;
105   UINT64 PrecisePC : 1;
106   UINT64 RestartablePC : 1;
107   UINT64 Reserved : 34;
108 } EFI_ARM_TLB_ERROR_STRUCTURE;
109 
110 typedef struct {
111   UINT64 ValidationBits : 16;
112   UINT64 TransactionType : 2;
113   UINT64 Operation : 4;
114   UINT64 Level : 3;
115   UINT64 ProcessorContextCorrupt : 1;
116   UINT64 Corrected : 1;
117   UINT64 PrecisePC : 1;
118   UINT64 RestartablePC : 1;
119   UINT64 ParticipationType : 2;
120   UINT64 TimeOut : 1;
121   UINT64 AddressSpace : 2;
122   UINT64 MemoryAddressAttributes : 8;
123   UINT64 AccessMode : 1;
124   UINT64 Reserved : 19;
125 } EFI_ARM_BUS_ERROR_STRUCTURE;
126 
127 typedef union {
128   EFI_ARM_CACHE_ERROR_STRUCTURE CacheError;
129   EFI_ARM_TLB_ERROR_STRUCTURE TlbError;
130   EFI_ARM_BUS_ERROR_STRUCTURE BusError;
131 } EFI_ARM_ERROR_INFORMATION_STRUCTURE;
132 
133 typedef struct {
134   UINT8 Version;
135   UINT8 Length;
136   UINT16 ValidationBits;
137   UINT8 Type;
138   UINT16 MultipleError;
139   UINT8 Flags;
140   EFI_ARM_ERROR_INFORMATION_STRUCTURE ErrorInformation;
141   UINT64 VirtualFaultAddress;
142   UINT64 PhysicalFaultAddress;
143 } __attribute__((packed, aligned(1))) EFI_ARM_ERROR_INFORMATION_ENTRY;
144 
145 ///
146 /// ARM Processor Context Information Structure
147 ///
148 typedef struct {
149   UINT16 Version;
150   UINT16 RegisterContextType;
151   UINT32 RegisterArraySize;
152 } EFI_ARM_CONTEXT_INFORMATION_HEADER;
153 
154 ///
155 /// ARM Processor Context Register Types
156 ///
157 #define EFI_ARM_CONTEXT_TYPE_AARCH32_GPR 0
158 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL1 1
159 #define EFI_ARM_CONTEXT_TYPE_AARCH32_EL2 2
160 #define EFI_ARM_CONTEXT_TYPE_AARCH32_SECURE 3
161 #define EFI_ARM_CONTEXT_TYPE_AARCH64_GPR 4
162 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL1 5
163 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL2 6
164 #define EFI_ARM_CONTEXT_TYPE_AARCH64_EL3 7
165 #define EFI_ARM_CONTEXT_TYPE_MISC 8
166 
167 typedef struct {
168   UINT32 R0;
169   UINT32 R1;
170   UINT32 R2;
171   UINT32 R3;
172   UINT32 R4;
173   UINT32 R5;
174   UINT32 R6;
175   UINT32 R7;
176   UINT32 R8;
177   UINT32 R9;
178   UINT32 R10;
179   UINT32 R11;
180   UINT32 R12;
181   UINT32 R13_sp;
182   UINT32 R14_lr;
183   UINT32 R15_pc;
184 } EFI_ARM_V8_AARCH32_GPR;
185 
186 typedef struct {
187   UINT32 Dfar;
188   UINT32 Dfsr;
189   UINT32 Ifar;
190   UINT32 Isr;
191   UINT32 Mair0;
192   UINT32 Mair1;
193   UINT32 Midr;
194   UINT32 Mpidr;
195   UINT32 Nmrr;
196   UINT32 Prrr;
197   UINT32 Sctlr_Ns;
198   UINT32 Spsr;
199   UINT32 Spsr_Abt;
200   UINT32 Spsr_Fiq;
201   UINT32 Spsr_Irq;
202   UINT32 Spsr_Svc;
203   UINT32 Spsr_Und;
204   UINT32 Tpidrprw;
205   UINT32 Tpidruro;
206   UINT32 Tpidrurw;
207   UINT32 Ttbcr;
208   UINT32 Ttbr0;
209   UINT32 Ttbr1;
210   UINT32 Dacr;
211 } EFI_ARM_AARCH32_EL1_CONTEXT_REGISTERS;
212 
213 typedef struct {
214   UINT32 Elr_Hyp;
215   UINT32 Hamair0;
216   UINT32 Hamair1;
217   UINT32 Hcr;
218   UINT32 Hcr2;
219   UINT32 Hdfar;
220   UINT32 Hifar;
221   UINT32 Hpfar;
222   UINT32 Hsr;
223   UINT32 Htcr;
224   UINT32 Htpidr;
225   UINT32 Httbr;
226   UINT32 Spsr_Hyp;
227   UINT32 Vtcr;
228   UINT32 Vttbr;
229   UINT32 Dacr32_El2;
230 } EFI_ARM_AARCH32_EL2_CONTEXT_REGISTERS;
231 
232 typedef struct {
233   UINT32 Sctlr_S;
234   UINT32 Spsr_Mon;
235 } EFI_ARM_AARCH32_SECURE_CONTEXT_REGISTERS;
236 
237 typedef struct {
238   UINT64 X0;
239   UINT64 X1;
240   UINT64 X2;
241   UINT64 X3;
242   UINT64 X4;
243   UINT64 X5;
244   UINT64 X6;
245   UINT64 X7;
246   UINT64 X8;
247   UINT64 X9;
248   UINT64 X10;
249   UINT64 X11;
250   UINT64 X12;
251   UINT64 X13;
252   UINT64 X14;
253   UINT64 X15;
254   UINT64 X16;
255   UINT64 X17;
256   UINT64 X18;
257   UINT64 X19;
258   UINT64 X20;
259   UINT64 X21;
260   UINT64 X22;
261   UINT64 X23;
262   UINT64 X24;
263   UINT64 X25;
264   UINT64 X26;
265   UINT64 X27;
266   UINT64 X28;
267   UINT64 X29;
268   UINT64 X30;
269   UINT64 Sp;
270 } EFI_ARM_V8_AARCH64_GPR;
271 
272 typedef struct {
273   UINT64 Elr_El1;
274   UINT64 Esr_El1;
275   UINT64 Far_El1;
276   UINT64 Isr_El1;
277   UINT64 Mair_El1;
278   UINT64 Midr_El1;
279   UINT64 Mpidr_El1;
280   UINT64 Sctlr_El1;
281   UINT64 Sp_El0;
282   UINT64 Sp_El1;
283   UINT64 Spsr_El1;
284   UINT64 Tcr_El1;
285   UINT64 Tpidr_El0;
286   UINT64 Tpidr_El1;
287   UINT64 Tpidrro_El0;
288   UINT64 Ttbr0_El1;
289   UINT64 Ttbr1_El1;
290 } EFI_ARM_AARCH64_EL1_CONTEXT_REGISTERS;
291 
292 typedef struct {
293   UINT64 Elr_El2;
294   UINT64 Esr_El2;
295   UINT64 Far_El2;
296   UINT64 Hacr_El2;
297   UINT64 Hcr_El2;
298   UINT64 Hpfar_El2;
299   UINT64 Mair_El2;
300   UINT64 Sctlr_El2;
301   UINT64 Sp_El2;
302   UINT64 Spsr_El2;
303   UINT64 Tcr_El2;
304   UINT64 Tpidr_El2;
305   UINT64 Ttbr0_El2;
306   UINT64 Vtcr_El2;
307   UINT64 Vttbr_El2;
308 } EFI_ARM_AARCH64_EL2_CONTEXT_REGISTERS;
309 
310 typedef struct {
311   UINT64 Elr_El3;
312   UINT64 Esr_El3;
313   UINT64 Far_El3;
314   UINT64 Mair_El3;
315   UINT64 Sctlr_El3;
316   UINT64 Sp_El3;
317   UINT64 Spsr_El3;
318   UINT64 Tcr_El3;
319   UINT64 Tpidr_El3;
320   UINT64 Ttbr0_El3;
321 } EFI_ARM_AARCH64_EL3_CONTEXT_REGISTERS;
322 
323 typedef struct {
324   UINT64 MrsOp2 : 3;
325   UINT64 MrsCrm : 4;
326   UINT64 MrsCrn : 4;
327   UINT64 MrsOp1 : 3;
328   UINT64 MrsO0 : 1;
329   UINT64 Value : 64;
330 } EFI_ARM_MISC_CONTEXT_REGISTER;
331 
332 json_object* cper_section_arm_to_ir(void* section, EFI_ERROR_SECTION_DESCRIPTOR* descriptor);
333 void ir_section_arm_to_cper(json_object* section, FILE* out);
334 
335 #endif