1 /* 2 // Copyright (c) 2018 Intel Corporation 3 // 4 // Licensed under the Apache License, Version 2.0 (the "License"); 5 // you may not use this file except in compliance with the License. 6 // You may obtain a copy of the License at 7 // 8 // http://www.apache.org/licenses/LICENSE-2.0 9 // 10 // Unless required by applicable law or agreed to in writing, software 11 // distributed under the License is distributed on an "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 // See the License for the specific language governing permissions and 14 // limitations under the License. 15 */ 16 17 #pragma once 18 19 #include <user_channel/user_layer.hpp> 20 enum class IPMINetfnIntelOEMGeneralCmd 21 { 22 cmdGetSmSignal = 0x14, 23 cmdSetSmSignal = 0x15, 24 cmdSetBIOSID = 0x26, 25 cmdGetOEMDeviceInfo = 0x27, 26 cmdSetColdRedundancyConfig = 0x2d, 27 cmdGetColdRedundancyConfig = 0x2e, 28 cmdGetAICSlotFRUIDSlotPosRecords = 0x31, 29 cmdSetSystemGUID = 0x41, 30 cmdDisableBMCSystemReset = 0x42, 31 cmdGetBMCResetDisables = 0x43, 32 cmdSendEmbeddedFWUpdStatus = 0x44, 33 cmdSetPowerRestoreDelay = 0x54, 34 cmdGetPowerRestoreDelay = 0x55, 35 cmdSetFaultIndication = 0x57, 36 cmdSetOEMUser2Activation = 0x5A, 37 cmdSetSpecialUserPassword = 0x5F, 38 cmdSetShutdownPolicy = 0x60, 39 cmdGetShutdownPolicy = 0x62, 40 cmdSetFanConfig = 0x89, 41 cmdGetFanConfig = 0x8a, 42 cmdSetFanSpeedOffset = 0x8c, 43 cmdGetFanSpeedOffset = 0x8d, 44 cmdSetDimmOffset = 0x8e, 45 cmdGetDimmOffset = 0x8f, 46 cmdSetFscParameter = 0x90, 47 cmdGetFscParameter = 0x91, 48 cmdGetChassisIdentifier = 0x92, 49 cmdReadBaseBoardProductId = 0x93, 50 cmdGetProcessorErrConfig = 0x9A, 51 cmdSetProcessorErrConfig = 0x9B, 52 cmdGetLEDStatus = 0xB0, 53 cmdControlBmcServices = 0xB1, 54 cmdGetBmcServiceStatus = 0xB2, 55 cmdMtmKeepAlive = 0xB5, 56 cmdGetNmiStatus = 0xE5, 57 cmdSetEfiBootOptions = 0xEA, 58 cmdGetEfiBootOptions = 0xEB, 59 cmdSetNmiStatus = 0xED, 60 }; 61 62 enum class IPMINetfnIntelOEMPlatformCmd 63 { 64 cmdCfgHostSerialPortSpeed = 0x90, 65 }; 66 67 enum class IPMIIntelOEMReturnCodes 68 { 69 ipmiCCPayloadActive = 0x80, 70 ipmiCCInvalidPCIESlotID = 0x80, 71 ipmiCCParameterNotSupported = 0x80, 72 ipmiCCPayloadAlreadyDeactivated = 0x80, 73 ipmiCCSetInProcess = 0x81, 74 ipmiCCPayloadDisable = 0x81, 75 ipmiCCLostArbitration = 0x81, 76 ipmiCCInvalidCablePortIndex = 0x81, 77 ipmiCCHealthStatusNotAvailable = 0x81, 78 ipmiCCBusError = 0x82, 79 ipmiCCReadOnly = 0x82, 80 ipmiCCWriteOnly = 0x82, 81 ipmiCCNoCablePresent = 0x82, 82 ipmiCCDataCollectionInProgress = 0x82, 83 ipmiCCPayloadActivationLimitReached = 0x82, 84 ipmiCCNACKOnWrite = 0x83, 85 ipmiCCDataCollectionFailed = 0x83, 86 ipmiCCCanNotActivateWithEncrption = 0x83, 87 ipmiCCCanNotActivateWithoutEncryption = 0x84, 88 ipmiCCInvalidChecksum = 0x85, 89 ipmiCCNoCabledPCIEPortsAvailable = 0xC2, 90 91 }; 92 93 enum class IPMIReturnCodeExt 94 { 95 ipmiCCInvalidLUN = 0xC2, 96 ipmiCCTimeout = 0xC3, 97 ipmiCCStorageLeak = 0xC4, 98 ipmiCCRequestDataTruncated = 0xC6, 99 ipmiCCRequestDataFieldLengthLimitExceeded = 0xC8, 100 ipmiCCCanNotReturnNumberOfRequestedDataBytes = 0xCA, 101 ipmiCCRequestSensorDataRecordNotFound = 0xCB, 102 ipmiCCDestinationUnavailable = 0xD3, 103 ipmiCCParamterNotSupportInPresentState = 0xD5, 104 }; 105 106 constexpr const uint8_t netfunIntelAppOEM = 0x3E; 107 static constexpr ipmi_netfn_t netfnIntcOEMGeneral = 108 NETFUN_NONE; // Netfun_none. In our platform, we use it as "intel oem 109 // general". The code is 0x30 110 111 // Intel OEM Platform code is 0x32 112 static constexpr ipmi_netfn_t netfnIntcOEMPlatform = NETFUN_OEM; 113 static constexpr const uint8_t maxBIOSIDLength = 0xFF; 114 static constexpr const uint8_t maxCPUNum = 4; 115 static constexpr const char* biosObjPath = "/xyz/openbmc_project/bios"; 116 static constexpr const char* biosIntf = 117 "xyz.openbmc_project.Inventory.Item.Bios"; 118 static constexpr const char* biosProp = "BiosId"; 119 120 static constexpr const char* powerRestoreDelayObjPath = 121 "/xyz/openbmc_project/control/power_restore_delay"; 122 static constexpr const char* powerRestoreDelayIntf = 123 "xyz.openbmc_project.Control.Power.RestoreDelay"; 124 static constexpr const char* powerRestoreDelayProp = "PowerRestoreDelay"; 125 static constexpr const char* processorErrConfigObjPath = 126 "/xyz/openbmc_project/control/processor_error_config"; 127 static constexpr const char* processorErrConfigIntf = 128 "xyz.openbmc_project.Control.Processor.ErrConfig"; 129 static constexpr const char* bmcResetDisablesPath = 130 "/xyz/openbmc_project/control/bmc_reset_disables"; 131 static constexpr const char* bmcResetDisablesIntf = 132 "xyz.openbmc_project.Control.ResetDisables"; 133 134 static constexpr const char* postCodesObjPath = 135 "/xyz/openbmc_project/State/Boot/PostCode"; 136 static constexpr const char* postCodesIntf = 137 "xyz.openbmc_project.State.Boot.PostCode"; 138 139 static constexpr const char* identifyLEDObjPath = 140 "/xyz/openbmc_project/led/physical/identify"; 141 static constexpr const char* ledIntf = "xyz.openbmc_project.Led.Physical"; 142 static constexpr const char* statusAmberObjPath = 143 "/xyz/openbmc_project/led/physical/status_amber"; 144 static constexpr const char* statusGreenObjPath = 145 "/xyz/openbmc_project/led/physical/status_green"; 146 147 static constexpr const uint8_t noShutdownOnOCOT = 0; 148 static constexpr const uint8_t shutdownOnOCOT = 1; 149 static constexpr const uint8_t noShutdownPolicySupported = 0; 150 static constexpr const uint8_t shutdownPolicySupported = 1; 151 static constexpr const char* oemShutdownPolicyIntf = 152 "com.intel.Control.OCOTShutdownPolicy"; 153 static constexpr const char* oemShutdownPolicyObjPath = 154 "/com/intel/control/ocotshutdown_policy_config"; 155 static constexpr const char* oemShutdownPolicyObjPathProp = "OCOTPolicy"; 156 157 static constexpr const char* fwGetEnvCmd = "/sbin/fw_printenv"; 158 static constexpr const char* fwSetEnvCmd = "/sbin/fw_setenv"; 159 static constexpr const char* fwHostSerailCfgEnvName = "hostserialcfg"; 160 161 constexpr const char* settingsBusName = "xyz.openbmc_project.Settings"; 162 163 static constexpr const uint8_t getHostSerialCfgCmd = 0; 164 static constexpr const uint8_t setHostSerialCfgCmd = 1; 165 166 // parameters: 167 // 0: host serial port 1 and 2 normal speed 168 // 1: host serial port 1 high spend, port 2 normal speed 169 // 2: host serial port 1 normal spend, port 2 high speed 170 // 3: host serial port 1 and 2 high speed 171 static constexpr const uint8_t HostSerialCfgParamMax = 3; 172 static constexpr uint8_t ipmiDefaultUserId = 2; 173 174 static constexpr const uint8_t selEvtTargetMask = 0xF0; 175 static constexpr const uint8_t selEvtTargetShift = 4; 176 177 static constexpr const uint8_t targetInstanceMask = 0x0E; 178 static constexpr const uint8_t targetInstanceShift = 1; 179 180 enum class IPMINetfnIntelOEMAppCmd 181 { 182 mdrStatus = 0x20, 183 mdrComplete = 0x21, 184 mdrEvent = 0x22, 185 mdrRead = 0x23, 186 mdrWrite = 0x24, 187 mdrLock = 0x25, 188 mdr2AgentStatus = 0x30, 189 mdr2GetDir = 0x31, 190 mdr2GetDataInfo = 0x32, 191 mdr2LockData = 0x33, 192 mdr2UnlockData = 0x34, 193 mdr2GetDataBlock = 0x35, 194 mdr2SendDir = 0x38, 195 mdr2SendDataInfoOffer = 0x39, 196 mdr2SendDataInfo = 0x3a, 197 mdr2DataStart = 0x3b, 198 mdr2DataDone = 0x3c, 199 mdr2SendDataBlock = 0x3d, 200 }; 201 202 enum class OEMDevEntityType 203 { 204 biosId, 205 devVer, 206 sdrVer, 207 }; 208 209 enum class FWUpdateTarget : uint8_t 210 { 211 targetBMC = 0x0, 212 targetBIOS = 0x1, 213 targetME = 0x2, 214 targetOEMEWS = 0x4, 215 }; 216 217 enum class CPUStatus 218 { 219 disabled = 0x0, 220 enabled = 0x1, 221 notPresent = 0x3, 222 }; 223 224 #pragma pack(push, 1) 225 struct GUIDData 226 { 227 uint8_t node1; 228 uint8_t node2; 229 uint8_t node3; 230 uint8_t node4; 231 uint8_t node5; 232 uint8_t node6; 233 uint8_t clock1; 234 uint8_t clock2; 235 uint8_t timeHigh1; 236 uint8_t timeHigh2; 237 uint8_t timeMid1; 238 uint8_t timeMid2; 239 uint8_t timeLow1; 240 uint8_t timeLow2; 241 uint8_t timeLow3; 242 uint8_t timeLow4; 243 }; 244 245 struct DeviceInfo 246 { 247 uint8_t biosIDLength; 248 uint8_t biosId[maxBIOSIDLength]; 249 }; 250 251 struct SetPowerRestoreDelayReq 252 { 253 uint8_t byteMSB; 254 uint8_t byteLSB; 255 }; 256 257 struct GetPowerRestoreDelayRes 258 { 259 uint8_t byteMSB; 260 uint8_t byteLSB; 261 }; 262 263 struct GetOemDeviceInfoReq 264 { 265 uint8_t entityType; 266 uint8_t countToRead; 267 uint8_t offset; 268 }; 269 270 struct GetOemDeviceInfoRes 271 { 272 uint8_t resDatalen; 273 uint8_t data[maxBIOSIDLength]; 274 }; 275 276 struct GetOEMShutdownPolicyRes 277 { 278 uint8_t policy; 279 uint8_t policySupport; 280 }; 281 282 struct SetFanConfigReq 283 { 284 uint8_t selectedProfile; 285 uint8_t flags; 286 // other parameters from previous generation are not supported 287 }; 288 struct CfgHostSerialReq 289 { 290 uint8_t command; 291 uint8_t parameter; 292 }; 293 #pragma pack(pop) 294 295 // 296 // Fault type enumeration 297 // 298 enum class RemoteFaultType 299 { 300 fan, // 0 301 temperature, // 1 302 power, // 2 303 driveslot, // 3 304 software, // 4 305 memory, // 5 306 max = 6 // 6 307 }; 308 309 // Enumeration for remote fault states as required by the HSC 310 // 311 enum class RemoteFaultState 312 { 313 // fault indicators 314 fanLEDs, 315 cpu1DimmLeds, 316 cpu2DimmLeds, 317 cpu3DimmLeds, 318 cpu4DimmLeds, 319 maxFaultState, 320 }; 321 322 enum class DimmFaultType 323 { 324 cpu1cpu2Dimm, 325 cpu3cpu4Dimm, 326 maxFaultGroup, 327 }; 328 329 enum class setFanProfileFlags : uint8_t 330 { 331 setFanProfile = 7, 332 setPerfAcousMode = 6, 333 // reserved [5:3] 334 performAcousSelect = 2 335 // reserved [1:0] 336 }; 337 338 enum class setFscParamFlags : uint8_t 339 { 340 tcontrol = 0x1, 341 pwmOffset = 0x2, 342 maxPwm = 0x3, 343 cfm = 0x4 344 }; 345 346 enum class dimmOffsetTypes : uint8_t 347 { 348 staticCltt = 0x0, 349 dimmPower = 0x2 350 }; 351 352 // FIXME: this stuff needs to be rewritten 353 enum IPMI_INTEL_OEM_RETURN_CODES 354 { 355 IPMI_CC_OEM_PAYLOAD_ACTIVE = 0x80, 356 IPMI_CC_OEM_INVALID_PCIE_SLOTID = 0x80, 357 IPMI_CC_OEM_PARAMETER_NOT_SUPPORTED = 0x80, 358 IPMI_CC_OEM_PAYLOAD_ALREADY_DEACTIVATED = 0x80, 359 IPMI_CC_OEM_SET_IN_PROCESS = 0x81, 360 IPMI_CC_OEM_PAYLOAD_DISABLE = 0x81, 361 IPMI_CC_OEM_LOST_ARBITRATION = 0x81, 362 IPMI_CC_OEM_INVALID_CABLE_PORT_INDEX = 0x81, 363 IPMI_CC_OEM_HEALTH_STATUS_NOT_AVAILABLE = 0x81, 364 IPMI_CC_OEM_BUS_ERROR = 0x82, 365 IPMI_CC_OEM_READ_ONLY = 0x82, 366 IPMI_CC_OEM_WRITE_ONLY = 0x82, 367 IPMI_CC_OEM_NO_CABLE_PRESENT = 0x82, 368 IPMI_CC_OEM_DATA_COLLECTION_IN_PROGRESS = 0x82, 369 IPMI_CC_OEM_PAYLOAD_ACTIVATION_LIMIT_REACH = 0x82, 370 IPMI_CC_OEM_NACK_ON_WRITE = 0x83, 371 IPMI_CC_OEM_DATA_COLLECTION_FAILED = 0x83, 372 IPMI_CC_OEM_CAN_NOT_ACTIVATE_WITH_ENCRYPTION = 0x83, 373 IPMI_CC_OEM_CAN_NOT_ACTIVATE_WITHOUT_ENCRYPTION = 0x84, 374 IPMI_CC_OEM_INVALID_CHECKSUM = 0x85, 375 IPMI_CC_OEM_NO_CABLED_PCIE_PORTS_AVAILABLE = 0xC2, 376 }; 377 378 enum IPMI_RETURN_CODE_EXT 379 { 380 IPMI_CC_INVALID_LUN = 0xC2, 381 IPMI_CC_STORGE_LEAK = 0xC4, 382 IPMI_CC_REQUEST_DATA_TRUNCATED = 0xC6, 383 IPMI_CC_REQUEST_DATA_FIELD_LENGTH_LIMIT_EXCEEDED = 0xC8, 384 IPMI_CC_CANNOT_RETURN_NUMBER_OF_REQUESTED_DATA_BYTES = 0xCA, 385 IPMI_CC_REQUEST_SENSOR_DATA_RECORD_NOT_FOUND = 0xCB, 386 IPMI_CC_DESTINATION_UNAVAILABLE = 0xD3, 387 IPMI_CC_PARAMETER_NOT_SUPPORT_IN_PRESENT_STATE = 0xD5, 388 }; 389 390 constexpr unsigned char NETFUN_INTEL_APP_OEM = 0x3E; 391 392 enum IPMI_NETFN_INTEL_OEM_APP_CMD 393 { 394 MDR_STATUS = 0x20, 395 MDR_COMPLETE = 0x21, 396 MDR_EVENT = 0x22, 397 MDR_READ = 0x23, 398 MDR_WRITE = 0x24, 399 MDR_LOCK = 0x25, 400 MDRII_AGENT_STATUS = 0x30, 401 MDRII_GET_DIR = 0x31, 402 MDRII_GET_DATA_INFO = 0x32, 403 MDRII_LOCK_DATA = 0x33, 404 MDRII_UNLOCK_DATA = 0x34, 405 MDRII_GET_DATA_BLOCK = 0x35, 406 MDRII_SEND_DIR = 0x38, 407 MDRII_SEND_DATA_INFO_OFFER = 0x39, 408 MDRII_SEND_DATA_INFO = 0x3a, 409 MDRII_DATA_START = 0x3b, 410 MDRII_DATA_DONE = 0x3c, 411 MDRII_SEND_DATA_BLOCK = 0x3d, 412 }; 413