1 /* 2 // Copyright (c) 2018 Intel Corporation 3 // 4 // Licensed under the Apache License, Version 2.0 (the "License"); 5 // you may not use this file except in compliance with the License. 6 // You may obtain a copy of the License at 7 // 8 // http://www.apache.org/licenses/LICENSE-2.0 9 // 10 // Unless required by applicable law or agreed to in writing, software 11 // distributed under the License is distributed on an "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 // See the License for the specific language governing permissions and 14 // limitations under the License. 15 */ 16 17 #pragma once 18 19 enum class IPMINetfnIntelOEMGeneralCmd 20 { 21 cmdSetBIOSID = 0x26, 22 cmdGetOEMDeviceInfo = 0x27, 23 cmdGetAICSlotFRUIDSlotPosRecords = 0x31, 24 cmdSetSystemGUID = 0x41, 25 cmdSetPowerRestoreDelay = 0x54, 26 cmdGetPowerRestoreDelay = 0x55, 27 cmdSetShutdownPolicy = 0x60, 28 cmdGetShutdownPolicy = 0x62, 29 cmdGetChassisIdentifier = 0x92, 30 cmdGetProcessorErrConfig = 0x9A, 31 cmdSetProcessorErrConfig = 0x9B, 32 }; 33 34 enum class IPMIIntelOEMReturnCodes 35 { 36 ipmiCCPayloadActive = 0x80, 37 ipmiCCInvalidPCIESlotID = 0x80, 38 ipmiCCParameterNotSupported = 0x80, 39 ipmiCCPayloadAlreadyDeactivated = 0x80, 40 ipmiCCSetInProcess = 0x81, 41 ipmiCCPayloadDisable = 0x81, 42 ipmiCCLostArbitration = 0x81, 43 ipmiCCInvalidCablePortIndex = 0x81, 44 ipmiCCHealthStatusNotAvailable = 0x81, 45 ipmiCCBusError = 0x82, 46 ipmiCCReadOnly = 0x82, 47 ipmiCCWriteOnly = 0x82, 48 ipmiCCNoCablePresent = 0x82, 49 ipmiCCDataCollectionInProgress = 0x82, 50 ipmiCCPayloadActivationLimitReached = 0x82, 51 ipmiCCNACKOnWrite = 0x83, 52 ipmiCCDataCollectionFailed = 0x83, 53 ipmiCCCanNotActivateWithEncrption = 0x83, 54 ipmiCCCanNotActivateWithoutEncryption = 0x84, 55 ipmiCCInvalidChecksum = 0x85, 56 ipmiCCNoCabledPCIEPortsAvailable = 0xC2, 57 58 }; 59 60 enum class IPMIReturnCodeExt 61 { 62 ipmiCCInvalidLUN = 0xC2, 63 ipmiCCTimeout = 0xC3, 64 ipmiCCStorageLeak = 0xC4, 65 ipmiCCRequestDataTruncated = 0xC6, 66 ipmiCCRequestDataFieldLengthLimitExceeded = 0xC8, 67 ipmiCCCanNotReturnNumberOfRequestedDataBytes = 0xCA, 68 ipmiCCRequestSensorDataRecordNotFound = 0xCB, 69 ipmiCCDestinationUnavailable = 0xD3, 70 ipmiCCParamterNotSupportInPresentState = 0xD5, 71 }; 72 73 constexpr const uint8_t netfunIntelAppOEM = 0x3E; 74 static constexpr ipmi_netfn_t netfnIntcOEMGeneral = 75 NETFUN_NONE; // Netfun_none. In our platform, we use it as "intel oem 76 // general". The code is 0x30 77 static constexpr const uint8_t maxBIOSIDLength = 0xFF; 78 static constexpr const uint8_t maxCPUNum = 4; 79 static constexpr const char* biosObjPath = "/xyz/openbmc_project/bios"; 80 static constexpr const char* biosIntf = 81 "xyz.openbmc_project.Inventory.Item.Bios"; 82 static constexpr const char* biosProp = "BiosId"; 83 84 static constexpr const char* powerRestoreDelayObjPath = 85 "/xyz/openbmc_project/control/power_restore_delay"; 86 static constexpr const char* powerRestoreDelayIntf = 87 "xyz.openbmc_project.Control.Power.RestoreDelay"; 88 static constexpr const char* powerRestoreDelayProp = "PowerRestoreDelay"; 89 static constexpr const char* processorErrConfigObjPath = 90 "/xyz/openbmc_project/control/processor_error_config"; 91 static constexpr const char* processorErrConfigIntf = 92 "xyz.openbmc_project.Control.Processor.ErrConfig"; 93 94 static constexpr const char* postCodesObjPath = 95 "/xyz/openbmc_project/State/Boot/PostCode"; 96 static constexpr const char* postCodesIntf = 97 "xyz.openbmc_project.State.Boot.PostCode"; 98 99 static constexpr const uint8_t noShutdownOnOCOT = 0; 100 static constexpr const uint8_t shutdownOnOCOT = 1; 101 static constexpr const uint8_t noShutdownPolicySupported = 0; 102 static constexpr const uint8_t shutdownPolicySupported = 1; 103 static constexpr const char* oemShutdownPolicyIntf = 104 "xyz.openbmc_project.Control.ShutdownPolicy"; 105 static constexpr const char* oemShutdownPolicyObjPath = 106 "/xyz/openbmc_project/control/shutdown_policy_config"; 107 static constexpr const char* oemShutdownPolicyObjPathProp = "Policy"; 108 109 enum class IPMINetfnIntelOEMAppCmd 110 { 111 mdrStatus = 0x20, 112 mdrComplete = 0x21, 113 mdrEvent = 0x22, 114 mdrRead = 0x23, 115 mdrWrite = 0x24, 116 mdrLock = 0x25, 117 mdr2AgentStatus = 0x30, 118 mdr2GetDir = 0x31, 119 mdr2GetDataInfo = 0x32, 120 mdr2LockData = 0x33, 121 mdr2UnlockData = 0x34, 122 mdr2GetDataBlock = 0x35, 123 mdr2SendDir = 0x38, 124 mdr2SendDataInfoOffer = 0x39, 125 mdr2SendDataInfo = 0x3a, 126 mdr2DataStart = 0x3b, 127 mdr2DataDone = 0x3c, 128 mdr2SendDataBlock = 0x3d, 129 }; 130 131 enum class OEMDevEntityType 132 { 133 biosId, 134 devVer, 135 sdrVer, 136 }; 137 138 #pragma pack(push, 1) 139 struct GUIDData 140 { 141 uint8_t node1; 142 uint8_t node2; 143 uint8_t node3; 144 uint8_t node4; 145 uint8_t node5; 146 uint8_t node6; 147 uint8_t clock1; 148 uint8_t clock2; 149 uint8_t timeHigh1; 150 uint8_t timeHigh2; 151 uint8_t timeMid1; 152 uint8_t timeMid2; 153 uint8_t timeLow1; 154 uint8_t timeLow2; 155 uint8_t timeLow3; 156 uint8_t timeLow4; 157 }; 158 159 struct DeviceInfo 160 { 161 uint8_t biosIDLength; 162 uint8_t biosId[maxBIOSIDLength]; 163 }; 164 165 struct SetPowerRestoreDelayReq 166 { 167 uint8_t byteMSB; 168 uint8_t byteLSB; 169 }; 170 171 struct GetPowerRestoreDelayRes 172 { 173 uint8_t byteMSB; 174 uint8_t byteLSB; 175 }; 176 177 struct GetOemDeviceInfoReq 178 { 179 uint8_t entityType; 180 uint8_t countToRead; 181 uint8_t offset; 182 }; 183 184 struct GetOemDeviceInfoRes 185 { 186 uint8_t resDatalen; 187 uint8_t data[maxBIOSIDLength]; 188 }; 189 190 struct SetProcessorErrConfigReq 191 { 192 uint8_t resetCfg; // Reset Configuration 193 // [0]: CATERR Reset Enabled 194 // 0b: Disabled 195 // 1b: Enabled 196 // [1]: ERR2 Reset Enabled 197 // 0b: Disabled 198 // 1b: Enabled 199 // [7:2]: Reserved 200 uint8_t reserved; // Reserved 201 uint8_t 202 resetErrorOccurrenceCounts; // Reset Error Occurrence Counts 203 //[0]: Reset CPU Error Counts 204 // 0b: Keep CPU Error Counts 205 // 1b: Reset all CPU Error Counts to zero 206 //[7:1]: Reserved 207 }; 208 209 struct GetProcessorErrConfigRes 210 { 211 uint8_t resetCfg; // Reset Configuration 212 // [0]: CATERR Reset Enabled 213 // 0b: Disabled 214 // 1b: Enabled 215 // [1]: ERR2 Reset Enabled 216 // 0b: Disabled 217 // 1b: Enabled 218 // [7:2]: Reserved 219 uint8_t reserved; // Reserved 220 char caterrStatus[maxCPUNum]; // for all CPUs including the non-legacy 221 // socket CPU CPU CATERR (Core Error) 222 // occurrence 223 // [5:0]: Error Occurrence Count 224 // [7:6]: CPU Status 225 // 00b: Disabled 226 // 01b: Enabled 227 // 11b: Not Present 228 }; 229 230 struct GetOEMShutdownPolicyRes 231 { 232 uint8_t policy; 233 uint8_t policySupport; 234 }; 235 #pragma pack(pop)