1 /* 2 * Copyright (c) 2018-present Facebook. All Rights Reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #pragma once 18 19 enum ipmi_fb_net_fns 20 { 21 NETFN_OEM_USB_DBG_REQ = 0x3C, 22 NETFN_OEM_USB_DBG_RES = 0x3D, 23 }; 24 25 // OEM Command Codes for USB basded Debug Card 26 enum oem_usb_dbg_cmds 27 { 28 CMD_OEM_USB_DBG_GET_FRAME_INFO = 0x1, 29 CMD_OEM_USB_DBG_GET_UPDATED_FRAMES = 0x2, 30 CMD_OEM_USB_DBG_GET_POST_DESC = 0x3, 31 CMD_OEM_USB_DBG_GET_GPIO_DESC = 0x4, 32 CMD_OEM_USB_DBG_GET_FRAME_DATA = 0x5, 33 CMD_OEM_USB_DBG_CTRL_PANEL = 0x6, 34 }; 35 36 // OEM Command Codes for FB 1S/2S servers 37 enum fb_oem_cmds 38 { 39 CMD_OEM_ADD_RAS_SEL = 0x10, 40 CMD_OEM_ADD_IMC_LOG = 0x11, 41 CMD_OEM_SET_MAC_ADDR = 0x18, 42 CMD_OEM_GET_MAC_ADDR = 0x19, 43 CMD_OEM_SET_PROC_INFO = 0x1A, 44 CMD_OEM_GET_PROC_INFO = 0x1B, 45 CMD_OEM_SET_DIMM_INFO = 0x1C, 46 CMD_OEM_GET_DIMM_INFO = 0x1D, 47 CMD_OEM_BYPASS_CMD = 0x34, 48 CMD_OEM_GET_BOARD_ID = 0x37, 49 CMD_OEM_GET_80PORT_RECORD = 0x49, 50 CMD_OEM_SET_BOOT_ORDER = 0x52, 51 CMD_OEM_GET_BOOT_ORDER = 0x53, 52 CMD_OEM_SET_MACHINE_CONFIG_INFO = 0x6A, 53 CMD_OEM_LEGACY_SET_PPR = 0x6E, 54 CMD_OEM_LEGACY_GET_PPR = 0x6F, 55 CMD_OEM_SET_POST_START = 0x73, 56 CMD_OEM_SET_POST_END = 0x74, 57 CMD_OEM_SET_PPIN_INFO = 0x77, 58 CMD_OEM_SET_ADR_TRIGGER = 0x7A, 59 CMD_OEM_GET_PLAT_INFO = 0x7E, 60 CMD_OEM_SET_SYSTEM_GUID = 0xEF, 61 CMD_OEM_GET_FW_INFO = 0xF2, 62 CMD_OEM_SLED_AC_CYCLE = 0xF3, 63 CMD_OEM_GET_PCIE_CONFIG = 0xF4, 64 CMD_OEM_SET_IMC_VERSION = 0xF5, 65 CMD_OEM_SET_FW_UPDATE_STATE = 0xF6, 66 CMD_OEM_GET_BIOS_FLASH_INFO = 0x55, 67 CMD_OEM_GET_PCIE_PORT_CONFIG = 0x80, 68 CMD_OEM_SET_PCIE_PORT_CONFIG = 0x81, 69 CMD_OEM_GET_TPM_PRESENCE = 0x82, 70 CMD_OEM_SET_TPM_PRESENCE = 0x83, 71 CMD_OEM_SET_BIOS_FLASH_INFO = 0x87, 72 CMD_OEM_SET_PPR = 0x90, 73 CMD_OEM_GET_PPR = 0x91, 74 CMD_OEM_SET_IPMB_OFFONLINE = 0xE6, 75 CMD_OEM_RISER_SENSOR_MON_CRL = 0xE7, 76 CMD_OEM_BBV_POWER_CYCLE = 0xE9, 77 CMD_OEM_CRASHDUMP = 0x70, 78 79 }; 80 81 // OEM Command Codes for QC 82 enum fb_oem_qc_cmds 83 { 84 CMD_OEM_Q_SET_PROC_INFO = 0x10, 85 CMD_OEM_Q_GET_PROC_INFO = 0x11, 86 CMD_OEM_Q_SET_DIMM_INFO = 0x12, 87 CMD_OEM_Q_GET_DIMM_INFO = 0x13, 88 CMD_OEM_Q_SET_DRIVE_INFO = 0x14, 89 CMD_OEM_Q_GET_DRIVE_INFO = 0x15, 90 }; 91 92 /* To handle the processor product 93 * name (ASCII code). */ 94 #define MAX_BUF 50 95 96 #define BMC_POS 0 97 #define SIZE_CPU_PPIN 8 98 #define SIZE_BOOT_ORDER 6 99 #define BOOT_MODE_UEFI 0x01 100 #define BOOT_MODE_CMOS_CLR 0x02 101 #define BOOT_MODE_FORCE_BOOT 0x04 102 #define BOOT_MODE_BOOT_FLAG 0x80 103 #define BIT_0 0x01 104 #define BIT_1 0x02 105 #define BIT_2 0x04 106 #define BIT_3 0x08 107 108 #define KEY_PROC_NAME "product_name" 109 #define KEY_BASIC_INFO "basic_info" 110 #define DIMM_TYPE "type" 111 #define DIMM_SPEED "speed" 112 #define JSON_DIMM_TYPE_FILE "/usr/share/lcd-debug/dimm_type.json" 113 #define JSON_OEM_DATA_FILE "/etc/oemData.json" 114 #define KEY_PPIN_INFO "mb_cpu_ppin" 115 #define KEY_MC_CONFIG "mb_machine_config" 116 #define KEY_MC_CHAS_TYPE "chassis_type" 117 #define KEY_MC_MB_TYPE "mb_type" 118 #define KEY_MC_PROC_CNT "processor_count" 119 #define KEY_MC_MEM_CNT "memory_count" 120 #define KEY_MC_HDD35_CNT "hdd35_count" 121 #define KEY_MC_HDD25_CNT "hdd25_count" 122 #define KEY_MC_RSR_TYPE "riser_type" 123 #define KEY_MC_PCIE_LOC "pcie_card_loc" 124 #define KEY_MC_SLOT1_TYPE "slot1_pcie_type" 125 #define KEY_MC_SLOT2_TYPE "slot2_pcie_type" 126 #define KEY_MC_SLOT3_TYPE "slot3_pcie_type" 127 #define KEY_MC_SLOT4_TYPE "slot4_pcie_type" 128 #define KEY_MC_AEP_CNT "aep_mem_count" 129 130 #define KEY_TS_SLED "timestamp_sled" 131 #define KEY_BOOT_ORDER "server_boot_order" 132 #define KEY_BOOT_MODE "boot_mode" 133 #define KEY_BOOT_SEQ "boot_sequence" 134 #define KEY_SYS_CONFIG "sys_config" 135 #define KEY_DIMM_INDEX "dimm_index" 136 #define KEY_DIMM_TYPE "dimm_type" 137 #define KEY_DIMM_SPEED "dimm_speed" 138 #define KEY_DIMM_SIZE "dimm_size" 139 #define KEY_PPR "ppr" 140 #define KEY_PPR_ACTION "ppr_row_action" 141 #define KEY_PPR_ROW_COUNT "ppr_row_count" 142 #define KEY_PPR_INDEX "ppr_index" 143 #define KEY_PPR_ROW_ADDR "ppr_row_addr" 144 #define KEY_PPR_HST_DATA "ppr_history_data" 145 #define CC_PARAM_NOT_SUPP_IN_CURR_STATE 0xD5 146 #define PPR_ROW_ADDR_LEN 8 147 #define PPR_HST_DATA_LEN 17 148 149 #define BOOT_SEQ_ARRAY_SIZE 10 150 151 const char* bootSeqDefine[] = {"USB_DEV", "NET_IPV4", "SATA_HDD", "SATA_CD", 152 "OTHER", "", "", "", 153 "", "NET_IPV6"}; 154 155 /* 156 Byte 2-6– Boot sequence 157 Bit 2:0 – boot device id 158 000b: USB device 159 001b: Network 160 010b: SATA HDD 161 011b: SATA-CDROM 162 100b: Other removable Device 163 Bit 7:3 – reserve for boot device special request 164 If Bit 2:0 is 001b (Network), Bit3 is IPv4/IPv6 order 165 Bit3=0b: IPv4 first 166 Bit3=1b: IPv6 first 167 */ 168 std::map<std::string, int> bootMap = {{"USB_DEV", 0}, {"NET_IPV4", 1}, 169 {"NET_IPV6", 9}, {"SATA_HDD", 2}, 170 {"SATA_CD", 3}, {"OTHER", 4}}; 171 172 std::map<size_t, std::string> dimmVenMap = { 173 {0xce, "Samsung"}, {0xad, "Hynix"}, {0x2c, "Micron"}}; 174 175 const char* chassisType[] = {"ORV1", "ORV2"}; 176 const char* mbType[] = {"SS", "DS", "TYPE3"}; 177 const char* riserType[] = {"NO_CARD", "2_SLOT", "3_SLOT"}; 178 const char* pcieType[] = {"ABSENT", "AVA1", "AVA2", "AVA3", 179 "AVA4", "Re-timer", "HBA", "OTHER"}; 180 181 enum fb_ppr_sel 182 { 183 PPR_ACTION = 1, 184 PPR_ROW_COUNT, 185 PPR_ROW_ADDR, 186 PPR_HISTORY_DATA, 187 }; 188 189 typedef struct 190 { 191 uint8_t chassis_type; // 00 - ORv1, 01 - ORv2 (FBTP) 192 uint8_t mb_type; // 00 - SS, 01 - DS, 02 - Type3 193 uint8_t proc_cnt; 194 uint8_t mem_cnt; 195 uint8_t hdd35_cnt; // 0/1 in FBTP, ff - unknown 196 uint8_t hdd25_cnt; // 0 for FBTP 197 uint8_t riser_type; // 00 - not installed, 01 - 2 slot, 02 - 3 slot 198 uint8_t pcie_card_loc; // Bit0 - Slot1 Present/Absent, Bit1 - Slot 2 199 // Present/Absent etc. 200 uint8_t slot1_pcie_type; // Always NIC for FBTP 201 uint8_t slot2_pcie_type; // 2-4: 00 - Absent, 01 - AVA 2 x m.2, 02 - AVA 202 // 3x m.2, 203 uint8_t slot3_pcie_type; // 03 - AVA 4 x m.2, 04 - Re-timer, 05 - HBA 204 uint8_t slot4_pcie_type; // 06 - Other flash cards (Intel, HGST), 205 // 80 - Unknown 206 uint8_t aep_mem_cnt; 207 } machineConfigInfo_t; 208 209 /* FB OEM QC commands data structures */ 210 211 #define NETFUN_FB_OEM_QC 0x36 212 213 #define KEY_Q_PROC_INFO "q_proc_info" 214 #define KEY_PROC_INDEX "proc_index" 215 #define KEY_Q_DIMM_INFO "q_dimm_info" 216 #define KEY_DIMM_INDEX "dimm_index" 217 #define KEY_Q_DRIVE_INFO "q_drive_info" 218 #define KEY_HDD_CTRL_TYPE "hdd_ctrl_type" 219 #define KEY_HDD_INDEX "hdd_index" 220 221 typedef struct 222 { 223 uint8_t mfrId[3]; 224 uint8_t procIndex; 225 uint8_t paramSel; 226 uint8_t data[]; 227 } qProcInfo_t; 228 229 typedef struct 230 { 231 uint8_t mfrId[3]; 232 uint8_t dimmIndex; 233 uint8_t paramSel; 234 uint8_t data[]; 235 } qDimmInfo_t; 236 237 typedef struct 238 { 239 uint8_t mfrId[3]; 240 uint8_t hddCtrlType; 241 uint8_t hddIndex; 242 uint8_t paramSel; 243 uint8_t data[]; 244 } qDriveInfo_t; 245 246 enum class BankType : uint8_t 247 { 248 mca = 0x01, 249 virt = 0x02, 250 cpuWdt = 0x03, 251 tcdx = 0x06, 252 cake = 0x07, 253 pie0 = 0x08, 254 iom = 0x09, 255 ccix = 0x0a, 256 cs = 0x0b, 257 pcieAer = 0x0c, 258 wdtReg = 0x0d, 259 ctrl = 0x80, 260 crdHdr = 0x81 261 }; 262 263 enum class CrdState 264 { 265 free = 0x01, 266 waitData = 0x02, 267 packing = 0x03 268 }; 269 270 enum class CrdCtrl 271 { 272 getState = 0x01, 273 finish = 0x02 274 }; 275 276 constexpr uint8_t ccmNum = 8; 277 constexpr uint8_t tcdxNum = 12; 278 constexpr uint8_t cakeNum = 6; 279 constexpr uint8_t pie0Num = 1; 280 constexpr uint8_t iomNum = 4; 281 constexpr uint8_t ccixNum = 4; 282 constexpr uint8_t csNum = 8; 283 284 #pragma pack(push, 1) 285 286 struct CrdCmdHdr 287 { 288 uint8_t version; 289 uint8_t reserved[3]; 290 }; 291 292 struct CrdBankHdr 293 { 294 BankType bankType; 295 uint8_t version; 296 union 297 { 298 struct 299 { 300 uint8_t bankId; 301 uint8_t coreId; 302 }; 303 uint8_t reserved[2]; 304 }; 305 }; 306 307 struct CrashDumpHdr 308 { 309 CrdCmdHdr cmdHdr; 310 CrdBankHdr bankHdr; 311 }; 312 313 // Type 0x01: MCA Bank 314 struct CrdMcaBank 315 { 316 uint64_t mcaCtrl; 317 uint64_t mcaSts; 318 uint64_t mcaAddr; 319 uint64_t mcaMisc0; 320 uint64_t mcaCtrlMask; 321 uint64_t mcaConfig; 322 uint64_t mcaIpid; 323 uint64_t mcaSynd; 324 uint64_t mcaDestat; 325 uint64_t mcaDeaddr; 326 uint64_t mcaMisc1; 327 }; 328 329 struct BankCorePair 330 { 331 uint8_t bankId; 332 uint8_t coreId; 333 }; 334 335 // Type 0x02: Virtual/Global Bank 336 struct CrdVirtualBankV2 337 { 338 uint32_t s5ResetSts; 339 uint32_t breakevent; 340 uint16_t mcaCount; 341 uint16_t procNum; 342 uint32_t apicId; 343 uint32_t eax; 344 uint32_t ebx; 345 uint32_t ecx; 346 uint32_t edx; 347 struct BankCorePair mcaList[]; 348 }; 349 350 struct CrdVirtualBankV3 351 { 352 uint32_t s5ResetSts; 353 uint32_t breakevent; 354 uint32_t rstSts; 355 uint16_t mcaCount; 356 uint16_t procNum; 357 uint32_t apicId; 358 uint32_t eax; 359 uint32_t ebx; 360 uint32_t ecx; 361 uint32_t edx; 362 struct BankCorePair mcaList[]; 363 }; 364 365 // Type 0x03: CPU/Data Fabric Watchdog Timer Bank 366 struct CrdCpuWdtBank 367 { 368 uint32_t hwAssertStsHi[ccmNum]; 369 uint32_t hwAssertStsLo[ccmNum]; 370 uint32_t origWdtAddrLogHi[ccmNum]; 371 uint32_t origWdtAddrLogLo[ccmNum]; 372 uint32_t hwAssertMskHi[ccmNum]; 373 uint32_t hwAssertMskLo[ccmNum]; 374 uint32_t origWdtAddrLogStat[ccmNum]; 375 }; 376 377 template <size_t N> 378 struct CrdHwAssertBank 379 { 380 uint32_t hwAssertStsHi[N]; 381 uint32_t hwAssertStsLo[N]; 382 uint32_t hwAssertMskHi[N]; 383 uint32_t hwAssertMskLo[N]; 384 }; 385 386 // Type 0x0C: PCIe AER Bank 387 struct CrdPcieAerBank 388 { 389 uint8_t bus; 390 uint8_t dev; 391 uint8_t fun; 392 uint16_t cmd; 393 uint16_t sts; 394 uint16_t slot; 395 uint8_t secondBus; 396 uint16_t vendorId; 397 uint16_t devId; 398 uint16_t classCodeLo; // Class Code 3 byte 399 uint8_t classCodeHi; 400 uint16_t secondSts; 401 uint16_t ctrl; 402 uint32_t uncorrErrSts; 403 uint32_t uncorrErrMsk; 404 uint32_t uncorrErrSeverity; 405 uint32_t corrErrSts; 406 uint32_t corrErrMsk; 407 uint32_t hdrLogDw0; 408 uint32_t hdrLogDw1; 409 uint32_t hdrLogDw2; 410 uint32_t hdrLogDw3; 411 uint32_t rootErrSts; 412 uint16_t corrErrSrcId; 413 uint16_t errSrcId; 414 uint32_t laneErrSts; 415 }; 416 417 // Type 0x0D: SMU/PSP/PTDMA Watchdog Timers Register Bank 418 struct CrdWdtRegBank 419 { 420 uint8_t nbio; 421 char name[32]; 422 uint32_t addr; 423 uint8_t count; 424 uint32_t data[]; 425 }; 426 427 // Type 0x81: Crashdump Header 428 struct CrdHdrBank 429 { 430 uint64_t ppin; 431 uint32_t ucodeVer; 432 uint32_t pmio; 433 }; 434 435 #pragma pack(pop) 436 437 const char* cpuInfoKey[] = {"", "product_name", "basic_info", 438 "type", "micro_code", "turbo_mode"}; 439 440 const char* dimmInfoKey[] = { 441 "", "location", "type", "speed", "part_name", 442 "serial_num", "manufacturer_id", "status", "present_bit"}; 443 444 const char* driveInfoKey[] = {"location", "serial_num", "model_name", 445 "fw_version", "capacity", "quantity", 446 "type", "wwn"}; 447 448 const char* ctrlTypeKey[] = {"bios", "expander", "lsi"}; 449