1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2019 Intel Corporation */ 3 4 // clang-format off 5 6 #ifndef __PECI_IOCTL_H 7 #define __PECI_IOCTL_H 8 9 #include <linux/ioctl.h> 10 #include <linux/types.h> 11 12 /* The PECI client's default address of 0x30 */ 13 #define PECI_BASE_ADDR 0x30 14 15 /* Max number of CPU clients */ 16 #define PECI_OFFSET_MAX 8 17 18 /* PECI read/write data buffer size max */ 19 #define PECI_BUFFER_SIZE 255 20 21 /* Device Specific Completion Code (CC) Definition */ 22 #define PECI_DEV_CC_SUCCESS 0x40 23 #define PECI_DEV_CC_NEED_RETRY 0x80 24 #define PECI_DEV_CC_OUT_OF_RESOURCE 0x81 25 #define PECI_DEV_CC_UNAVAIL_RESOURCE 0x82 26 #define PECI_DEV_CC_INVALID_REQ 0x90 27 #define PECI_DEV_CC_MCA_ERROR 0x91 28 #define PECI_DEV_CC_CATASTROPHIC_MCA_ERROR 0x93 29 #define PECI_DEV_CC_FATAL_MCA_DETECTED 0x94 30 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB 0x98 31 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_IERR 0x9B 32 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_MCA 0x9C 33 34 /* Completion Code mask to check retry needs */ 35 #define PECI_DEV_CC_RETRY_CHECK_MASK 0xf0 36 37 #define PECI_DEV_RETRY_TIMEOUT msecs_to_jiffies(700) 38 #define PECI_DEV_RETRY_INTERVAL_MIN_MSEC 1 39 #define PECI_DEV_RETRY_INTERVAL_MAX_MSEC 128 40 #define PECI_DEV_RETRY_BIT 0x01 41 42 /** 43 * enum peci_cmd - PECI client commands 44 * @PECI_CMD_XFER: raw PECI transfer 45 * @PECI_CMD_PING: ping, a required message for all PECI devices 46 * @PECI_CMD_GET_DIB: get DIB (Device Info Byte) 47 * @PECI_CMD_GET_TEMP: get maximum die temperature 48 * @PECI_CMD_RD_PKG_CFG: read access to the PCS (Package Configuration Space) 49 * @PECI_CMD_WR_PKG_CFG: write access to the PCS (Package Configuration Space) 50 * @PECI_CMD_RD_IA_MSR: read access to MSRs (Model Specific Registers) 51 * @PECI_CMD_WR_IA_MSR: write access to MSRs (Model Specific Registers) 52 * @PECI_CMD_RD_IA_MSREX: read access to MSRs (Model Specific Registers) 53 * @PECI_CMD_RD_PCI_CFG: sideband read access to the PCI configuration space 54 * maintained in downstream devices external to the processor 55 * @PECI_CMD_WR_PCI_CFG: sideband write access to the PCI configuration space 56 * maintained in downstream devices external to the processor 57 * @PECI_CMD_RD_PCI_CFG_LOCAL: sideband read access to the PCI configuration 58 * space that resides within the processor 59 * @PECI_CMD_WR_PCI_CFG_LOCAL: sideband write access to the PCI configuration 60 * space that resides within the processor 61 * 62 * Available commands depend on client's PECI revision. 63 */ 64 enum peci_cmd { 65 PECI_CMD_XFER = 0, 66 PECI_CMD_PING, 67 PECI_CMD_GET_DIB, 68 PECI_CMD_GET_TEMP, 69 PECI_CMD_RD_PKG_CFG, 70 PECI_CMD_WR_PKG_CFG, 71 PECI_CMD_RD_IA_MSR, 72 PECI_CMD_WR_IA_MSR, 73 PECI_CMD_RD_IA_MSREX, 74 PECI_CMD_RD_PCI_CFG, 75 PECI_CMD_WR_PCI_CFG, 76 PECI_CMD_RD_PCI_CFG_LOCAL, 77 PECI_CMD_WR_PCI_CFG_LOCAL, 78 PECI_CMD_RD_END_PT_CFG, 79 PECI_CMD_WR_END_PT_CFG, 80 PECI_CMD_CRASHDUMP_DISC, 81 PECI_CMD_CRASHDUMP_GET_FRAME, 82 PECI_CMD_MAX 83 }; 84 85 /** 86 * struct peci_xfer_msg - raw PECI transfer command 87 * @addr; address of the client 88 * @tx_len: number of data to be written in bytes 89 * @rx_len: number of data to be read in bytes 90 * @tx_buf: data to be written, or NULL 91 * @rx_buf: data to be read, or NULL 92 * 93 * raw PECI transfer 94 */ 95 struct peci_xfer_msg { 96 __u8 addr; 97 __u8 tx_len; 98 __u8 rx_len; 99 __u8 padding; 100 __u8 *tx_buf; 101 __u8 *rx_buf; 102 } __attribute__((__packed__)); 103 104 /** 105 * struct peci_ping_msg - ping command 106 * @addr: address of the client 107 * 108 * Ping() is a required message for all PECI devices. This message is used to 109 * enumerate devices or determine if a device has been removed, been 110 * powered-off, etc. 111 */ 112 struct peci_ping_msg { 113 __u8 addr; 114 __u8 padding[3]; 115 } __attribute__((__packed__)); 116 117 /** 118 * struct peci_get_dib_msg - GetDIB command 119 * @addr: address of the client 120 * @dib: DIB data to be read 121 * 122 * The processor PECI client implementation of GetDIB() includes an 8-byte 123 * response and provides information regarding client revision number and the 124 * number of supported domains. All processor PECI clients support the GetDIB() 125 * command. 126 */ 127 struct peci_get_dib_msg { 128 #define PECI_GET_DIB_WR_LEN 1 129 #define PECI_GET_DIB_RD_LEN 8 130 #define PECI_GET_DIB_CMD 0xf7 131 132 __u8 addr; 133 __u8 padding[3]; 134 __u64 dib; 135 } __attribute__((__packed__)); 136 137 /** 138 * struct peci_get_temp_msg - GetTemp command 139 * @addr: address of the client 140 * @temp_raw: raw temperature data to be read 141 * 142 * The GetTemp() command is used to retrieve the maximum die temperature from a 143 * target PECI address. The temperature is used by the external thermal 144 * management system to regulate the temperature on the die. The data is 145 * returned as a negative value representing the number of degrees centigrade 146 * below the maximum processor junction temperature. 147 */ 148 struct peci_get_temp_msg { 149 #define PECI_GET_TEMP_WR_LEN 1 150 #define PECI_GET_TEMP_RD_LEN 2 151 #define PECI_GET_TEMP_CMD 0x01 152 153 __u8 addr; 154 __u8 padding; 155 __s16 temp_raw; 156 } __attribute__((__packed__)); 157 158 /** 159 * struct peci_rd_pkg_cfg_msg - RdPkgConfig command 160 * @addr: address of the client 161 * @index: encoding index for the requested service 162 * @param: specific data being requested 163 * @rx_len: number of data to be read in bytes 164 * @cc: completion code 165 * @pkg_config: package config data to be read 166 * 167 * The RdPkgConfig() command provides read access to the Package Configuration 168 * Space (PCS) within the processor, including various power and thermal 169 * management functions. Typical PCS read services supported by the processor 170 * may include access to temperature data, energy status, run time information, 171 * DIMM temperatures and so on. 172 */ 173 struct peci_rd_pkg_cfg_msg { 174 #define PECI_RDPKGCFG_WRITE_LEN 5 175 #define PECI_RDPKGCFG_READ_LEN_BASE 1 176 #define PECI_RDPKGCFG_CMD 0xa1 177 178 __u8 addr; 179 __u8 index; 180 #define PECI_MBX_INDEX_CPU_ID 0 /* Package Identifier Read */ 181 #define PECI_MBX_INDEX_VR_DEBUG 1 /* VR Debug */ 182 #define PECI_MBX_INDEX_PKG_TEMP_READ 2 /* Package Temperature Read */ 183 #define PECI_MBX_INDEX_ENERGY_COUNTER 3 /* Energy counter */ 184 #define PECI_MBX_INDEX_ENERGY_STATUS 4 /* DDR Energy Status */ 185 #define PECI_MBX_INDEX_WAKE_MODE_BIT 5 /* "Wake on PECI" Mode bit */ 186 #define PECI_MBX_INDEX_EPI 6 /* Efficient Performance Indication */ 187 #define PECI_MBX_INDEX_PKG_RAPL_PERF 8 /* Pkg RAPL Performance Status Read */ 188 #define PECI_MBX_INDEX_PER_CORE_DTS_TEMP 9 /* Per Core DTS Temperature Read */ 189 #define PECI_MBX_INDEX_DTS_MARGIN 10 /* DTS thermal margin */ 190 #define PECI_MBX_INDEX_SKT_PWR_THRTL_DUR 11 /* Socket Power Throttled Duration */ 191 #define PECI_MBX_INDEX_CFG_TDP_CONTROL 12 /* TDP Config Control */ 192 #define PECI_MBX_INDEX_CFG_TDP_LEVELS 13 /* TDP Config Levels */ 193 #define PECI_MBX_INDEX_DDR_DIMM_TEMP 14 /* DDR DIMM Temperature */ 194 #define PECI_MBX_INDEX_CFG_ICCMAX 15 /* Configurable ICCMAX */ 195 #define PECI_MBX_INDEX_TEMP_TARGET 16 /* Temperature Target Read */ 196 #define PECI_MBX_INDEX_CURR_CFG_LIMIT 17 /* Current Config Limit */ 197 #define PECI_MBX_INDEX_DIMM_TEMP_READ 20 /* Package Thermal Status Read */ 198 #define PECI_MBX_INDEX_DRAM_IMC_TMP_READ 22 /* DRAM IMC Temperature Read */ 199 #define PECI_MBX_INDEX_DDR_CH_THERM_STAT 23 /* DDR Channel Thermal Status */ 200 #define PECI_MBX_INDEX_PKG_POWER_LIMIT1 26 /* Package Power Limit1 */ 201 #define PECI_MBX_INDEX_PKG_POWER_LIMIT2 27 /* Package Power Limit2 */ 202 #define PECI_MBX_INDEX_TDP 28 /* Thermal design power minimum */ 203 #define PECI_MBX_INDEX_TDP_HIGH 29 /* Thermal design power maximum */ 204 #define PECI_MBX_INDEX_TDP_UNITS 30 /* Units for power/energy registers */ 205 #define PECI_MBX_INDEX_RUN_TIME 31 /* Accumulated Run Time */ 206 #define PECI_MBX_INDEX_CONSTRAINED_TIME 32 /* Thermally Constrained Time Read */ 207 #define PECI_MBX_INDEX_TURBO_RATIO 33 /* Turbo Activation Ratio */ 208 #define PECI_MBX_INDEX_DDR_RAPL_PL1 34 /* DDR RAPL PL1 */ 209 #define PECI_MBX_INDEX_DDR_PWR_INFO_HIGH 35 /* DRAM Power Info Read (high) */ 210 #define PECI_MBX_INDEX_DDR_PWR_INFO_LOW 36 /* DRAM Power Info Read (low) */ 211 #define PECI_MBX_INDEX_DDR_RAPL_PL2 37 /* DDR RAPL PL2 */ 212 #define PECI_MBX_INDEX_DDR_RAPL_STATUS 38 /* DDR RAPL Performance Status */ 213 #define PECI_MBX_INDEX_DDR_HOT_ABSOLUTE 43 /* DDR Hottest Dimm Absolute Temp */ 214 #define PECI_MBX_INDEX_DDR_HOT_RELATIVE 44 /* DDR Hottest Dimm Relative Temp */ 215 #define PECI_MBX_INDEX_DDR_THROTTLE_TIME 45 /* DDR Throttle Time */ 216 #define PECI_MBX_INDEX_DDR_THERM_STATUS 46 /* DDR Thermal Status */ 217 #define PECI_MBX_INDEX_TIME_AVG_TEMP 47 /* Package time-averaged temperature */ 218 #define PECI_MBX_INDEX_TURBO_RATIO_LIMIT 49 /* Turbo Ratio Limit Read */ 219 #define PECI_MBX_INDEX_HWP_AUTO_OOB 53 /* HWP Autonomous Out-of-band */ 220 #define PECI_MBX_INDEX_DDR_WARM_BUDGET 55 /* DDR Warm Power Budget */ 221 #define PECI_MBX_INDEX_DDR_HOT_BUDGET 56 /* DDR Hot Power Budget */ 222 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM3 57 /* Package/Psys Power Limit3 */ 223 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM1 58 /* Package/Psys Power Limit1 */ 224 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM2 59 /* Package/Psys Power Limit2 */ 225 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM4 60 /* Package/Psys Power Limit4 */ 226 #define PECI_MBX_INDEX_PERF_LIMIT_REASON 65 /* Performance Limit Reasons */ 227 228 __u16 param; 229 /* When index is PECI_MBX_INDEX_CPU_ID */ 230 #define PECI_PKG_ID_CPU_ID 0x0000 /* CPUID Info */ 231 #define PECI_PKG_ID_PLATFORM_ID 0x0001 /* Platform ID */ 232 #define PECI_PKG_ID_UNCORE_ID 0x0002 /* Uncore Device ID */ 233 #define PECI_PKG_ID_MAX_THREAD_ID 0x0003 /* Max Thread ID */ 234 #define PECI_PKG_ID_MICROCODE_REV 0x0004 /* CPU Microcode Update Revision */ 235 #define PECI_PKG_ID_MACHINE_CHECK_STATUS 0x0005 /* Machine Check Status */ 236 237 __u8 rx_len; 238 __u8 cc; 239 __u8 padding[2]; 240 __u8 pkg_config[4]; 241 } __attribute__((__packed__)); 242 243 /** 244 * struct peci_wr_pkg_cfg_msg - WrPkgConfig command 245 * @addr: address of the client 246 * @index: encoding index for the requested service 247 * @param: specific data being requested 248 * @tx_len: number of data to be written in bytes 249 * @cc: completion code 250 * @value: package config data to be written 251 * 252 * The WrPkgConfig() command provides write access to the Package Configuration 253 * Space (PCS) within the processor, including various power and thermal 254 * management functions. Typical PCS write services supported by the processor 255 * may include power limiting, thermal averaging constant programming and so 256 * on. 257 */ 258 struct peci_wr_pkg_cfg_msg { 259 #define PECI_WRPKGCFG_WRITE_LEN_BASE 6 260 #define PECI_WRPKGCFG_READ_LEN 1 261 #define PECI_WRPKGCFG_CMD 0xa5 262 263 __u8 addr; 264 __u8 index; 265 #define PECI_MBX_INDEX_DIMM_AMBIENT 19 266 #define PECI_MBX_INDEX_DIMM_TEMP 24 267 268 __u16 param; 269 __u8 tx_len; 270 __u8 cc; 271 __u8 padding[2]; 272 __u32 value; 273 } __attribute__((__packed__)); 274 275 /** 276 * struct peci_rd_ia_msr_msg - RdIAMSR command 277 * @addr: address of the client 278 * @thread_id: ID of the specific logical processor 279 * @address: address of MSR to read from 280 * @cc: completion code 281 * @value: data to be read 282 * 283 * The RdIAMSR() PECI command provides read access to Model Specific Registers 284 * (MSRs) defined in the processor's Intel Architecture (IA). 285 */ 286 struct peci_rd_ia_msr_msg { 287 #define PECI_RDIAMSR_WRITE_LEN 5 288 #define PECI_RDIAMSR_READ_LEN 9 289 #define PECI_RDIAMSR_CMD 0xb1 290 291 __u8 addr; 292 __u8 thread_id; 293 __u16 address; 294 __u8 cc; 295 __u8 padding[3]; 296 __u64 value; 297 } __attribute__((__packed__)); 298 299 /** 300 * struct peci_wr_ia_msr_msg - WrIAMSR command 301 * @addr: address of the client 302 * @thread_id: ID of the specific logical processor 303 * @address: address of MSR to write to 304 * @tx_len: number of data to be written in bytes 305 * @cc: completion code 306 * @value: data to be written 307 * 308 * The WrIAMSR() PECI command provides write access to Model Specific Registers 309 * (MSRs) defined in the processor's Intel Architecture (IA). 310 */ 311 struct peci_wr_ia_msr_msg { 312 #define PECI_WRIAMSR_CMD 0xb5 313 314 __u8 addr; 315 __u8 thread_id; 316 __u16 address; 317 __u8 tx_len; 318 __u8 cc; 319 __u8 padding[2]; 320 __u64 value; 321 } __attribute__((__packed__)); 322 323 /** 324 * struct peci_rd_ia_msrex_msg - RdIAMSREX command 325 * @addr: address of the client 326 * @thread_id: ID of the specific logical processor 327 * @address: address of MSR to read from 328 * @cc: completion code 329 * @value: data to be read 330 * 331 * The RdIAMSREX() PECI command provides read access to Model Specific 332 * Registers (MSRs) defined in the processor's Intel Architecture (IA). 333 * The differences between RdIAMSREX() and RdIAMSR() are that: 334 * (1)RdIAMSR() can only read MC registers, RdIAMSREX() can read all MSRs 335 * (2)thread_id of RdIAMSR() is u8, thread_id of RdIAMSREX() is u16 336 */ 337 struct peci_rd_ia_msrex_msg { 338 #define PECI_RDIAMSREX_WRITE_LEN 6 339 #define PECI_RDIAMSREX_READ_LEN 9 340 #define PECI_RDIAMSREX_CMD 0xd1 341 342 __u8 addr; 343 __u8 padding0; 344 __u16 thread_id; 345 __u16 address; 346 __u8 cc; 347 __u8 padding1; 348 __u64 value; 349 } __attribute__((__packed__)); 350 351 /** 352 * struct peci_rd_pci_cfg_msg - RdPCIConfig command 353 * @addr: address of the client 354 * @bus: PCI bus number 355 * @device: PCI device number 356 * @function: specific function to read from 357 * @reg: specific register to read from 358 * @cc: completion code 359 * @pci_config: config data to be read 360 * 361 * The RdPCIConfig() command provides sideband read access to the PCI 362 * configuration space maintained in downstream devices external to the 363 * processor. 364 */ 365 struct peci_rd_pci_cfg_msg { 366 #define PECI_RDPCICFG_WRITE_LEN 6 367 #define PECI_RDPCICFG_READ_LEN 5 368 #define PECI_RDPCICFG_READ_LEN_MAX 24 369 #define PECI_RDPCICFG_CMD 0x61 370 371 __u8 addr; 372 __u8 bus; 373 #define PECI_PCI_BUS0_CPU0 0x00 374 #define PECI_PCI_BUS0_CPU1 0x80 375 #define PECI_PCI_CPUBUSNO_BUS 0x00 376 #define PECI_PCI_CPUBUSNO_DEV 0x08 377 #define PECI_PCI_CPUBUSNO_FUNC 0x02 378 #define PECI_PCI_CPUBUSNO 0xcc 379 #define PECI_PCI_CPUBUSNO_1 0xd0 380 #define PECI_PCI_CPUBUSNO_VALID 0xd4 381 382 __u8 device; 383 __u8 function; 384 __u16 reg; 385 __u8 cc; 386 __u8 padding[1]; 387 __u8 pci_config[4]; 388 } __attribute__((__packed__)); 389 390 /** 391 * struct peci_wr_pci_cfg_msg - WrPCIConfig command 392 * @addr: address of the client 393 * @bus: PCI bus number 394 * @device: PCI device number 395 * @function: specific function to write to 396 * @reg: specific register to write to 397 * @tx_len: number of data to be written in bytes 398 * @cc: completion code 399 * @pci_config: config data to be written 400 * 401 * The RdPCIConfig() command provides sideband write access to the PCI 402 * configuration space maintained in downstream devices external to the 403 * processor. 404 */ 405 struct peci_wr_pci_cfg_msg { 406 #define PECI_WRPCICFG_CMD 0x65 407 408 __u8 addr; 409 __u8 bus; 410 __u8 device; 411 __u8 function; 412 __u16 reg; 413 __u8 tx_len; 414 __u8 cc; 415 __u8 pci_config[4]; 416 } __attribute__((__packed__)); 417 418 /** 419 * struct peci_rd_pci_cfg_local_msg - RdPCIConfigLocal command 420 * @addr: address of the client 421 * @bus: PCI bus number 422 * @device: PCI device number 423 * @function: specific function to read from 424 * @reg: specific register to read from 425 * @rx_len: number of data to be read in bytes 426 * @cc: completion code 427 * @pci_config: config data to be read 428 * 429 * The RdPCIConfigLocal() command provides sideband read access to the PCI 430 * configuration space that resides within the processor. This includes all 431 * processor IIO and uncore registers within the PCI configuration space. 432 */ 433 struct peci_rd_pci_cfg_local_msg { 434 #define PECI_RDPCICFGLOCAL_WRITE_LEN 5 435 #define PECI_RDPCICFGLOCAL_READ_LEN_BASE 1 436 #define PECI_RDPCICFGLOCAL_CMD 0xe1 437 438 __u8 addr; 439 __u8 bus; 440 __u8 device; 441 __u8 function; 442 __u16 reg; 443 __u8 rx_len; 444 __u8 cc; 445 __u8 pci_config[4]; 446 } __attribute__((__packed__)); 447 448 /** 449 * struct peci_wr_pci_cfg_local_msg - WrPCIConfigLocal command 450 * @addr: address of the client 451 * @bus: PCI bus number 452 * @device: PCI device number 453 * @function: specific function to read from 454 * @reg: specific register to read from 455 * @tx_len: number of data to be written in bytes 456 * @cc: completion code 457 * @value: config data to be written 458 * 459 * The WrPCIConfigLocal() command provides sideband write access to the PCI 460 * configuration space that resides within the processor. PECI originators can 461 * access this space even before BIOS enumeration of the system buses. 462 */ 463 struct peci_wr_pci_cfg_local_msg { 464 #define PECI_WRPCICFGLOCAL_WRITE_LEN_BASE 6 465 #define PECI_WRPCICFGLOCAL_READ_LEN 1 466 #define PECI_WRPCICFGLOCAL_CMD 0xe5 467 468 __u8 addr; 469 __u8 bus; 470 __u8 device; 471 __u8 function; 472 __u16 reg; 473 __u8 tx_len; 474 __u8 cc; 475 __u32 value; 476 } __attribute__((__packed__)); 477 478 struct peci_rd_end_pt_cfg_msg { 479 #define PECI_RDENDPTCFG_PCI_WRITE_LEN 12 480 #define PECI_RDENDPTCFG_MMIO_D_WRITE_LEN 14 481 #define PECI_RDENDPTCFG_MMIO_Q_WRITE_LEN 18 482 #define PECI_RDENDPTCFG_READ_LEN_BASE 1 483 #define PECI_RDENDPTCFG_CMD 0xc1 484 485 __u8 addr; 486 __u8 msg_type; 487 #define PECI_ENDPTCFG_TYPE_LOCAL_PCI 0x03 488 #define PECI_ENDPTCFG_TYPE_PCI 0x04 489 #define PECI_ENDPTCFG_TYPE_MMIO 0x05 490 491 union { 492 struct { 493 __u8 seg; 494 __u8 bus; 495 __u8 device; 496 __u8 function; 497 __u16 reg; 498 } pci_cfg; 499 struct { 500 __u8 seg; 501 __u8 bus; 502 __u8 device; 503 __u8 function; 504 __u8 bar; 505 __u8 addr_type; 506 #define PECI_ENDPTCFG_ADDR_TYPE_PCI 0x04 507 #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_D 0x05 508 #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_Q 0x06 509 510 __u64 offset; 511 } mmio; 512 } params; 513 __u8 rx_len; 514 __u8 cc; 515 __u8 padding[2]; 516 __u8 data[8]; 517 } __attribute__((__packed__)); 518 519 struct peci_wr_end_pt_cfg_msg { 520 #define PECI_WRENDPTCFG_PCI_WRITE_LEN_BASE 13 521 #define PECI_WRENDPTCFG_MMIO_D_WRITE_LEN_BASE 15 522 #define PECI_WRENDPTCFG_MMIO_Q_WRITE_LEN_BASE 19 523 #define PECI_WRENDPTCFG_READ_LEN 1 524 #define PECI_WRENDPTCFG_CMD 0xc5 525 526 __u8 addr; 527 __u8 msg_type; 528 /* See msg_type in struct peci_rd_end_pt_cfg_msg */ 529 530 union { 531 struct { 532 __u8 seg; 533 __u8 bus; 534 __u8 device; 535 __u8 function; 536 __u16 reg; 537 } pci_cfg; 538 struct { 539 __u8 seg; 540 __u8 bus; 541 __u8 device; 542 __u8 function; 543 __u8 bar; 544 __u8 addr_type; 545 /* See addr_type in struct peci_rd_end_pt_cfg_msg */ 546 547 __u64 offset; 548 } mmio; 549 } params; 550 __u8 tx_len; 551 __u8 cc; 552 __u8 padding[2]; 553 __u64 value; 554 } __attribute__((__packed__)); 555 556 /* Crashdump Agent */ 557 #define PECI_CRASHDUMP_CORE 0x00 558 #define PECI_CRASHDUMP_TOR 0x01 559 560 /* Crashdump Agent Param */ 561 #define PECI_CRASHDUMP_PAYLOAD_SIZE 0x00 562 563 /* Crashdump Agent Data Param */ 564 #define PECI_CRASHDUMP_AGENT_ID 0x00 565 #define PECI_CRASHDUMP_AGENT_PARAM 0x01 566 567 struct peci_crashdump_disc_msg { 568 __u8 addr; 569 __u8 subopcode; 570 #define PECI_CRASHDUMP_ENABLED 0x00 571 #define PECI_CRASHDUMP_NUM_AGENTS 0x01 572 #define PECI_CRASHDUMP_AGENT_DATA 0x02 573 574 __u8 cc; 575 __u8 param0; 576 __u16 param1; 577 __u8 param2; 578 __u8 rx_len; 579 __u8 data[8]; 580 } __attribute__((__packed__)); 581 582 struct peci_crashdump_get_frame_msg { 583 #define PECI_CRASHDUMP_DISC_WRITE_LEN 9 584 #define PECI_CRASHDUMP_DISC_READ_LEN_BASE 1 585 #define PECI_CRASHDUMP_DISC_VERSION 0 586 #define PECI_CRASHDUMP_DISC_OPCODE 1 587 #define PECI_CRASHDUMP_GET_FRAME_WRITE_LEN 10 588 #define PECI_CRASHDUMP_GET_FRAME_READ_LEN_BASE 1 589 #define PECI_CRASHDUMP_GET_FRAME_VERSION 0 590 #define PECI_CRASHDUMP_GET_FRAME_OPCODE 3 591 #define PECI_CRASHDUMP_CMD 0x71 592 593 __u8 addr; 594 __u8 padding0; 595 __u16 param0; 596 __u16 param1; 597 __u16 param2; 598 __u8 rx_len; 599 __u8 cc; 600 __u8 padding1[2]; 601 __u8 data[16]; 602 } __attribute__((__packed__)); 603 604 #define PECI_IOC_BASE 0xb7 605 606 #define PECI_IOC_XFER \ 607 _IOWR(PECI_IOC_BASE, PECI_CMD_XFER, struct peci_xfer_msg) 608 609 #define PECI_IOC_PING \ 610 _IOWR(PECI_IOC_BASE, PECI_CMD_PING, struct peci_ping_msg) 611 612 #define PECI_IOC_GET_DIB \ 613 _IOWR(PECI_IOC_BASE, PECI_CMD_GET_DIB, struct peci_get_dib_msg) 614 615 #define PECI_IOC_GET_TEMP \ 616 _IOWR(PECI_IOC_BASE, PECI_CMD_GET_TEMP, struct peci_get_temp_msg) 617 618 #define PECI_IOC_RD_PKG_CFG \ 619 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PKG_CFG, struct peci_rd_pkg_cfg_msg) 620 621 #define PECI_IOC_WR_PKG_CFG \ 622 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PKG_CFG, struct peci_wr_pkg_cfg_msg) 623 624 #define PECI_IOC_RD_IA_MSR \ 625 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSR, struct peci_rd_ia_msr_msg) 626 627 #define PECI_IOC_WR_IA_MSR \ 628 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_IA_MSR, struct peci_wr_ia_msr_msg) 629 630 #define PECI_IOC_RD_IA_MSREX \ 631 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSREX, struct peci_rd_ia_msrex_msg) 632 633 #define PECI_IOC_RD_PCI_CFG \ 634 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG, struct peci_rd_pci_cfg_msg) 635 636 #define PECI_IOC_WR_PCI_CFG \ 637 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG, struct peci_wr_pci_cfg_msg) 638 639 #define PECI_IOC_RD_PCI_CFG_LOCAL \ 640 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG_LOCAL, \ 641 struct peci_rd_pci_cfg_local_msg) 642 643 #define PECI_IOC_WR_PCI_CFG_LOCAL \ 644 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG_LOCAL, \ 645 struct peci_wr_pci_cfg_local_msg) 646 647 #define PECI_IOC_RD_END_PT_CFG \ 648 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_END_PT_CFG, \ 649 struct peci_rd_end_pt_cfg_msg) 650 651 #define PECI_IOC_WR_END_PT_CFG \ 652 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_END_PT_CFG, \ 653 struct peci_wr_end_pt_cfg_msg) 654 655 #define PECI_IOC_CRASHDUMP_DISC \ 656 _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_DISC, \ 657 struct peci_crashdump_disc_msg) 658 659 #define PECI_IOC_CRASHDUMP_GET_FRAME \ 660 _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_GET_FRAME, \ 661 struct peci_crashdump_get_frame_msg) 662 663 #endif /* __PECI_IOCTL_H */ 664 // clang-format on 665