1fb64f45dSJoel Stanley /* SPDX-License-Identifier: GPL-2.0 */ 2b9122030SJae Hyun Yoo /* Copyright (c) 2018-2019 Intel Corporation */ 3fb64f45dSJoel Stanley 4fb64f45dSJoel Stanley // clang-format off 5*d02ad49eSPatrick Williams // NOLINTBEGIN 6fb64f45dSJoel Stanley 7fb64f45dSJoel Stanley #ifndef __PECI_IOCTL_H 8fb64f45dSJoel Stanley #define __PECI_IOCTL_H 9fb64f45dSJoel Stanley 10ec77caa4SEd Tanous #ifdef __cplusplus 11ec77caa4SEd Tanous extern "C" { 12ec77caa4SEd Tanous #endif 13ec77caa4SEd Tanous 14fb64f45dSJoel Stanley #include <linux/ioctl.h> 15fb64f45dSJoel Stanley #include <linux/types.h> 16fb64f45dSJoel Stanley 17b9122030SJae Hyun Yoo /* The PECI client's default address of 0x30 */ 18b9122030SJae Hyun Yoo #define PECI_BASE_ADDR 0x30 19fb64f45dSJoel Stanley 20b9122030SJae Hyun Yoo /* Max number of CPU clients */ 21b9122030SJae Hyun Yoo #define PECI_OFFSET_MAX 8 22fb64f45dSJoel Stanley 23b9122030SJae Hyun Yoo /* PECI read/write data buffer size max */ 24b9122030SJae Hyun Yoo #define PECI_BUFFER_SIZE 255 25fb64f45dSJoel Stanley 26b9122030SJae Hyun Yoo /* Device Specific Completion Code (CC) Definition */ 27b9122030SJae Hyun Yoo #define PECI_DEV_CC_SUCCESS 0x40 28b9122030SJae Hyun Yoo #define PECI_DEV_CC_NEED_RETRY 0x80 29b9122030SJae Hyun Yoo #define PECI_DEV_CC_OUT_OF_RESOURCE 0x81 30b9122030SJae Hyun Yoo #define PECI_DEV_CC_UNAVAIL_RESOURCE 0x82 31b9122030SJae Hyun Yoo #define PECI_DEV_CC_INVALID_REQ 0x90 32b9122030SJae Hyun Yoo #define PECI_DEV_CC_MCA_ERROR 0x91 33b9122030SJae Hyun Yoo #define PECI_DEV_CC_CATASTROPHIC_MCA_ERROR 0x93 34b9122030SJae Hyun Yoo #define PECI_DEV_CC_FATAL_MCA_DETECTED 0x94 35b9122030SJae Hyun Yoo #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB 0x98 36b9122030SJae Hyun Yoo #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_IERR 0x9B 37b9122030SJae Hyun Yoo #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_MCA 0x9C 38fb64f45dSJoel Stanley 39b9122030SJae Hyun Yoo /* Completion Code mask to check retry needs */ 40b9122030SJae Hyun Yoo #define PECI_DEV_CC_RETRY_CHECK_MASK 0xf0 41fb64f45dSJoel Stanley 42b9122030SJae Hyun Yoo #define PECI_DEV_RETRY_TIMEOUT msecs_to_jiffies(700) 43b9122030SJae Hyun Yoo #define PECI_DEV_RETRY_INTERVAL_MIN_MSEC 1 44b9122030SJae Hyun Yoo #define PECI_DEV_RETRY_INTERVAL_MAX_MSEC 128 45b9122030SJae Hyun Yoo #define PECI_DEV_RETRY_BIT 0x01 46fb64f45dSJoel Stanley 47b9122030SJae Hyun Yoo /** 48b9122030SJae Hyun Yoo * enum peci_cmd - PECI client commands 49b9122030SJae Hyun Yoo * @PECI_CMD_XFER: raw PECI transfer 50b9122030SJae Hyun Yoo * @PECI_CMD_PING: ping, a required message for all PECI devices 51b9122030SJae Hyun Yoo * @PECI_CMD_GET_DIB: get DIB (Device Info Byte) 52b9122030SJae Hyun Yoo * @PECI_CMD_GET_TEMP: get maximum die temperature 53b9122030SJae Hyun Yoo * @PECI_CMD_RD_PKG_CFG: read access to the PCS (Package Configuration Space) 54b9122030SJae Hyun Yoo * @PECI_CMD_WR_PKG_CFG: write access to the PCS (Package Configuration Space) 55b9122030SJae Hyun Yoo * @PECI_CMD_RD_IA_MSR: read access to MSRs (Model Specific Registers) 56b9122030SJae Hyun Yoo * @PECI_CMD_WR_IA_MSR: write access to MSRs (Model Specific Registers) 57b9122030SJae Hyun Yoo * @PECI_CMD_RD_IA_MSREX: read access to MSRs (Model Specific Registers) 58b9122030SJae Hyun Yoo * @PECI_CMD_RD_PCI_CFG: sideband read access to the PCI configuration space 59b9122030SJae Hyun Yoo * maintained in downstream devices external to the processor 60b9122030SJae Hyun Yoo * @PECI_CMD_WR_PCI_CFG: sideband write access to the PCI configuration space 61b9122030SJae Hyun Yoo * maintained in downstream devices external to the processor 62b9122030SJae Hyun Yoo * @PECI_CMD_RD_PCI_CFG_LOCAL: sideband read access to the PCI configuration 63b9122030SJae Hyun Yoo * space that resides within the processor 64b9122030SJae Hyun Yoo * @PECI_CMD_WR_PCI_CFG_LOCAL: sideband write access to the PCI configuration 65b9122030SJae Hyun Yoo * space that resides within the processor 66b9122030SJae Hyun Yoo * 67b9122030SJae Hyun Yoo * Available commands depend on client's PECI revision. 68b9122030SJae Hyun Yoo */ 69fb64f45dSJoel Stanley enum peci_cmd { 70fb64f45dSJoel Stanley PECI_CMD_XFER = 0, 71fb64f45dSJoel Stanley PECI_CMD_PING, 72fb64f45dSJoel Stanley PECI_CMD_GET_DIB, 73fb64f45dSJoel Stanley PECI_CMD_GET_TEMP, 74fb64f45dSJoel Stanley PECI_CMD_RD_PKG_CFG, 75fb64f45dSJoel Stanley PECI_CMD_WR_PKG_CFG, 76fb64f45dSJoel Stanley PECI_CMD_RD_IA_MSR, 77fb64f45dSJoel Stanley PECI_CMD_WR_IA_MSR, 78b9122030SJae Hyun Yoo PECI_CMD_RD_IA_MSREX, 79fb64f45dSJoel Stanley PECI_CMD_RD_PCI_CFG, 80fb64f45dSJoel Stanley PECI_CMD_WR_PCI_CFG, 81fb64f45dSJoel Stanley PECI_CMD_RD_PCI_CFG_LOCAL, 82fb64f45dSJoel Stanley PECI_CMD_WR_PCI_CFG_LOCAL, 83b9122030SJae Hyun Yoo PECI_CMD_RD_END_PT_CFG, 84b9122030SJae Hyun Yoo PECI_CMD_WR_END_PT_CFG, 85fb64f45dSJoel Stanley PECI_CMD_CRASHDUMP_DISC, 86fb64f45dSJoel Stanley PECI_CMD_CRASHDUMP_GET_FRAME, 87fb64f45dSJoel Stanley PECI_CMD_MAX 88fb64f45dSJoel Stanley }; 89fb64f45dSJoel Stanley 90b9122030SJae Hyun Yoo /** 91b9122030SJae Hyun Yoo * struct peci_xfer_msg - raw PECI transfer command 92b9122030SJae Hyun Yoo * @addr; address of the client 93b9122030SJae Hyun Yoo * @tx_len: number of data to be written in bytes 94b9122030SJae Hyun Yoo * @rx_len: number of data to be read in bytes 95b9122030SJae Hyun Yoo * @tx_buf: data to be written, or NULL 96b9122030SJae Hyun Yoo * @rx_buf: data to be read, or NULL 97b9122030SJae Hyun Yoo * 98b9122030SJae Hyun Yoo * raw PECI transfer 99b9122030SJae Hyun Yoo */ 100b9122030SJae Hyun Yoo struct peci_xfer_msg { 101b9122030SJae Hyun Yoo __u8 addr; 102b9122030SJae Hyun Yoo __u8 tx_len; 103b9122030SJae Hyun Yoo __u8 rx_len; 104b9122030SJae Hyun Yoo __u8 padding; 105b9122030SJae Hyun Yoo __u8 *tx_buf; 106b9122030SJae Hyun Yoo __u8 *rx_buf; 107b9122030SJae Hyun Yoo } __attribute__((__packed__)); 108b9122030SJae Hyun Yoo 109b9122030SJae Hyun Yoo /** 110b9122030SJae Hyun Yoo * struct peci_ping_msg - ping command 111b9122030SJae Hyun Yoo * @addr: address of the client 112b9122030SJae Hyun Yoo * 113b9122030SJae Hyun Yoo * Ping() is a required message for all PECI devices. This message is used to 114b9122030SJae Hyun Yoo * enumerate devices or determine if a device has been removed, been 115b9122030SJae Hyun Yoo * powered-off, etc. 116b9122030SJae Hyun Yoo */ 117fb64f45dSJoel Stanley struct peci_ping_msg { 118fb64f45dSJoel Stanley __u8 addr; 119b9122030SJae Hyun Yoo __u8 padding[3]; 120fb64f45dSJoel Stanley } __attribute__((__packed__)); 121fb64f45dSJoel Stanley 122b9122030SJae Hyun Yoo /** 123b9122030SJae Hyun Yoo * struct peci_get_dib_msg - GetDIB command 124b9122030SJae Hyun Yoo * @addr: address of the client 125b9122030SJae Hyun Yoo * @dib: DIB data to be read 126b9122030SJae Hyun Yoo * 127b9122030SJae Hyun Yoo * The processor PECI client implementation of GetDIB() includes an 8-byte 128b9122030SJae Hyun Yoo * response and provides information regarding client revision number and the 129b9122030SJae Hyun Yoo * number of supported domains. All processor PECI clients support the GetDIB() 130b9122030SJae Hyun Yoo * command. 131b9122030SJae Hyun Yoo */ 132fb64f45dSJoel Stanley struct peci_get_dib_msg { 133b9122030SJae Hyun Yoo #define PECI_GET_DIB_WR_LEN 1 134b9122030SJae Hyun Yoo #define PECI_GET_DIB_RD_LEN 8 135b9122030SJae Hyun Yoo #define PECI_GET_DIB_CMD 0xf7 136b9122030SJae Hyun Yoo 137fb64f45dSJoel Stanley __u8 addr; 138b9122030SJae Hyun Yoo __u8 padding[3]; 139b9122030SJae Hyun Yoo __u64 dib; 140fb64f45dSJoel Stanley } __attribute__((__packed__)); 141fb64f45dSJoel Stanley 142b9122030SJae Hyun Yoo /** 143b9122030SJae Hyun Yoo * struct peci_get_temp_msg - GetTemp command 144b9122030SJae Hyun Yoo * @addr: address of the client 145b9122030SJae Hyun Yoo * @temp_raw: raw temperature data to be read 146b9122030SJae Hyun Yoo * 147b9122030SJae Hyun Yoo * The GetTemp() command is used to retrieve the maximum die temperature from a 148b9122030SJae Hyun Yoo * target PECI address. The temperature is used by the external thermal 149b9122030SJae Hyun Yoo * management system to regulate the temperature on the die. The data is 150b9122030SJae Hyun Yoo * returned as a negative value representing the number of degrees centigrade 151b9122030SJae Hyun Yoo * below the maximum processor junction temperature. 152b9122030SJae Hyun Yoo */ 153fb64f45dSJoel Stanley struct peci_get_temp_msg { 154b9122030SJae Hyun Yoo #define PECI_GET_TEMP_WR_LEN 1 155b9122030SJae Hyun Yoo #define PECI_GET_TEMP_RD_LEN 2 156b9122030SJae Hyun Yoo #define PECI_GET_TEMP_CMD 0x01 157b9122030SJae Hyun Yoo 158fb64f45dSJoel Stanley __u8 addr; 159b9122030SJae Hyun Yoo __u8 padding; 160fb64f45dSJoel Stanley __s16 temp_raw; 161fb64f45dSJoel Stanley } __attribute__((__packed__)); 162fb64f45dSJoel Stanley 163b9122030SJae Hyun Yoo /** 164b9122030SJae Hyun Yoo * struct peci_rd_pkg_cfg_msg - RdPkgConfig command 165b9122030SJae Hyun Yoo * @addr: address of the client 166b9122030SJae Hyun Yoo * @index: encoding index for the requested service 167b9122030SJae Hyun Yoo * @param: specific data being requested 168b9122030SJae Hyun Yoo * @rx_len: number of data to be read in bytes 169b9122030SJae Hyun Yoo * @cc: completion code 170b9122030SJae Hyun Yoo * @pkg_config: package config data to be read 171b9122030SJae Hyun Yoo * 172b9122030SJae Hyun Yoo * The RdPkgConfig() command provides read access to the Package Configuration 173b9122030SJae Hyun Yoo * Space (PCS) within the processor, including various power and thermal 174b9122030SJae Hyun Yoo * management functions. Typical PCS read services supported by the processor 175b9122030SJae Hyun Yoo * may include access to temperature data, energy status, run time information, 176b9122030SJae Hyun Yoo * DIMM temperatures and so on. 177b9122030SJae Hyun Yoo */ 178fb64f45dSJoel Stanley struct peci_rd_pkg_cfg_msg { 179b9122030SJae Hyun Yoo #define PECI_RDPKGCFG_WRITE_LEN 5 180b9122030SJae Hyun Yoo #define PECI_RDPKGCFG_READ_LEN_BASE 1 181b9122030SJae Hyun Yoo #define PECI_RDPKGCFG_CMD 0xa1 182b9122030SJae Hyun Yoo 183fb64f45dSJoel Stanley __u8 addr; 184fb64f45dSJoel Stanley __u8 index; 185b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CPU_ID 0 /* Package Identifier Read */ 186b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_VR_DEBUG 1 /* VR Debug */ 187b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_TEMP_READ 2 /* Package Temperature Read */ 188b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_ENERGY_COUNTER 3 /* Energy counter */ 189b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_ENERGY_STATUS 4 /* DDR Energy Status */ 190b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_WAKE_MODE_BIT 5 /* "Wake on PECI" Mode bit */ 191b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_EPI 6 /* Efficient Performance Indication */ 192b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_RAPL_PERF 8 /* Pkg RAPL Performance Status Read */ 193b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PER_CORE_DTS_TEMP 9 /* Per Core DTS Temperature Read */ 194b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DTS_MARGIN 10 /* DTS thermal margin */ 195b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_SKT_PWR_THRTL_DUR 11 /* Socket Power Throttled Duration */ 196b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CFG_TDP_CONTROL 12 /* TDP Config Control */ 197b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CFG_TDP_LEVELS 13 /* TDP Config Levels */ 198b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_DIMM_TEMP 14 /* DDR DIMM Temperature */ 199b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CFG_ICCMAX 15 /* Configurable ICCMAX */ 200b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TEMP_TARGET 16 /* Temperature Target Read */ 201b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CURR_CFG_LIMIT 17 /* Current Config Limit */ 202b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DIMM_TEMP_READ 20 /* Package Thermal Status Read */ 203b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DRAM_IMC_TMP_READ 22 /* DRAM IMC Temperature Read */ 204b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_CH_THERM_STAT 23 /* DDR Channel Thermal Status */ 205b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_POWER_LIMIT1 26 /* Package Power Limit1 */ 206b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_POWER_LIMIT2 27 /* Package Power Limit2 */ 207b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TDP 28 /* Thermal design power minimum */ 208b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TDP_HIGH 29 /* Thermal design power maximum */ 209b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TDP_UNITS 30 /* Units for power/energy registers */ 210b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_RUN_TIME 31 /* Accumulated Run Time */ 211b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_CONSTRAINED_TIME 32 /* Thermally Constrained Time Read */ 212b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TURBO_RATIO 33 /* Turbo Activation Ratio */ 213b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_RAPL_PL1 34 /* DDR RAPL PL1 */ 214b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_PWR_INFO_HIGH 35 /* DRAM Power Info Read (high) */ 215b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_PWR_INFO_LOW 36 /* DRAM Power Info Read (low) */ 216b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_RAPL_PL2 37 /* DDR RAPL PL2 */ 217b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_RAPL_STATUS 38 /* DDR RAPL Performance Status */ 218b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_HOT_ABSOLUTE 43 /* DDR Hottest Dimm Absolute Temp */ 219b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_HOT_RELATIVE 44 /* DDR Hottest Dimm Relative Temp */ 220b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_THROTTLE_TIME 45 /* DDR Throttle Time */ 221b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_THERM_STATUS 46 /* DDR Thermal Status */ 222b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TIME_AVG_TEMP 47 /* Package time-averaged temperature */ 223b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_TURBO_RATIO_LIMIT 49 /* Turbo Ratio Limit Read */ 224b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_HWP_AUTO_OOB 53 /* HWP Autonomous Out-of-band */ 225b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_WARM_BUDGET 55 /* DDR Warm Power Budget */ 226b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DDR_HOT_BUDGET 56 /* DDR Hot Power Budget */ 227b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM3 57 /* Package/Psys Power Limit3 */ 228b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM1 58 /* Package/Psys Power Limit1 */ 229b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM2 59 /* Package/Psys Power Limit2 */ 230b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM4 60 /* Package/Psys Power Limit4 */ 231b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_PERF_LIMIT_REASON 65 /* Performance Limit Reasons */ 232b9122030SJae Hyun Yoo 233fb64f45dSJoel Stanley __u16 param; 234b9122030SJae Hyun Yoo /* When index is PECI_MBX_INDEX_CPU_ID */ 235b9122030SJae Hyun Yoo #define PECI_PKG_ID_CPU_ID 0x0000 /* CPUID Info */ 236b9122030SJae Hyun Yoo #define PECI_PKG_ID_PLATFORM_ID 0x0001 /* Platform ID */ 237b9122030SJae Hyun Yoo #define PECI_PKG_ID_UNCORE_ID 0x0002 /* Uncore Device ID */ 238b9122030SJae Hyun Yoo #define PECI_PKG_ID_MAX_THREAD_ID 0x0003 /* Max Thread ID */ 239b9122030SJae Hyun Yoo #define PECI_PKG_ID_MICROCODE_REV 0x0004 /* CPU Microcode Update Revision */ 240b9122030SJae Hyun Yoo #define PECI_PKG_ID_MACHINE_CHECK_STATUS 0x0005 /* Machine Check Status */ 241b9122030SJae Hyun Yoo 242fb64f45dSJoel Stanley __u8 rx_len; 243b9122030SJae Hyun Yoo __u8 cc; 244b9122030SJae Hyun Yoo __u8 padding[2]; 245fb64f45dSJoel Stanley __u8 pkg_config[4]; 246fb64f45dSJoel Stanley } __attribute__((__packed__)); 247fb64f45dSJoel Stanley 248b9122030SJae Hyun Yoo /** 249b9122030SJae Hyun Yoo * struct peci_wr_pkg_cfg_msg - WrPkgConfig command 250b9122030SJae Hyun Yoo * @addr: address of the client 251b9122030SJae Hyun Yoo * @index: encoding index for the requested service 252b9122030SJae Hyun Yoo * @param: specific data being requested 253b9122030SJae Hyun Yoo * @tx_len: number of data to be written in bytes 254b9122030SJae Hyun Yoo * @cc: completion code 255b9122030SJae Hyun Yoo * @value: package config data to be written 256b9122030SJae Hyun Yoo * 257b9122030SJae Hyun Yoo * The WrPkgConfig() command provides write access to the Package Configuration 258b9122030SJae Hyun Yoo * Space (PCS) within the processor, including various power and thermal 259b9122030SJae Hyun Yoo * management functions. Typical PCS write services supported by the processor 260b9122030SJae Hyun Yoo * may include power limiting, thermal averaging constant programming and so 261b9122030SJae Hyun Yoo * on. 262b9122030SJae Hyun Yoo */ 263fb64f45dSJoel Stanley struct peci_wr_pkg_cfg_msg { 264b9122030SJae Hyun Yoo #define PECI_WRPKGCFG_WRITE_LEN_BASE 6 265b9122030SJae Hyun Yoo #define PECI_WRPKGCFG_READ_LEN 1 266b9122030SJae Hyun Yoo #define PECI_WRPKGCFG_CMD 0xa5 267b9122030SJae Hyun Yoo 268fb64f45dSJoel Stanley __u8 addr; 269fb64f45dSJoel Stanley __u8 index; 270b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DIMM_AMBIENT 19 271b9122030SJae Hyun Yoo #define PECI_MBX_INDEX_DIMM_TEMP 24 272b9122030SJae Hyun Yoo 273fb64f45dSJoel Stanley __u16 param; 274fb64f45dSJoel Stanley __u8 tx_len; 275b9122030SJae Hyun Yoo __u8 cc; 276b9122030SJae Hyun Yoo __u8 padding[2]; 277fb64f45dSJoel Stanley __u32 value; 278fb64f45dSJoel Stanley } __attribute__((__packed__)); 279fb64f45dSJoel Stanley 280b9122030SJae Hyun Yoo /** 281b9122030SJae Hyun Yoo * struct peci_rd_ia_msr_msg - RdIAMSR command 282b9122030SJae Hyun Yoo * @addr: address of the client 283b9122030SJae Hyun Yoo * @thread_id: ID of the specific logical processor 284b9122030SJae Hyun Yoo * @address: address of MSR to read from 285b9122030SJae Hyun Yoo * @cc: completion code 286b9122030SJae Hyun Yoo * @value: data to be read 287b9122030SJae Hyun Yoo * 288b9122030SJae Hyun Yoo * The RdIAMSR() PECI command provides read access to Model Specific Registers 289b9122030SJae Hyun Yoo * (MSRs) defined in the processor's Intel Architecture (IA). 290b9122030SJae Hyun Yoo */ 291fb64f45dSJoel Stanley struct peci_rd_ia_msr_msg { 292b9122030SJae Hyun Yoo #define PECI_RDIAMSR_WRITE_LEN 5 293b9122030SJae Hyun Yoo #define PECI_RDIAMSR_READ_LEN 9 294b9122030SJae Hyun Yoo #define PECI_RDIAMSR_CMD 0xb1 295b9122030SJae Hyun Yoo 296fb64f45dSJoel Stanley __u8 addr; 297fb64f45dSJoel Stanley __u8 thread_id; 298fb64f45dSJoel Stanley __u16 address; 299b9122030SJae Hyun Yoo __u8 cc; 300b9122030SJae Hyun Yoo __u8 padding[3]; 301fb64f45dSJoel Stanley __u64 value; 302fb64f45dSJoel Stanley } __attribute__((__packed__)); 303fb64f45dSJoel Stanley 304b9122030SJae Hyun Yoo /** 305b9122030SJae Hyun Yoo * struct peci_wr_ia_msr_msg - WrIAMSR command 306b9122030SJae Hyun Yoo * @addr: address of the client 307b9122030SJae Hyun Yoo * @thread_id: ID of the specific logical processor 308b9122030SJae Hyun Yoo * @address: address of MSR to write to 309b9122030SJae Hyun Yoo * @tx_len: number of data to be written in bytes 310b9122030SJae Hyun Yoo * @cc: completion code 311b9122030SJae Hyun Yoo * @value: data to be written 312b9122030SJae Hyun Yoo * 313b9122030SJae Hyun Yoo * The WrIAMSR() PECI command provides write access to Model Specific Registers 314b9122030SJae Hyun Yoo * (MSRs) defined in the processor's Intel Architecture (IA). 315b9122030SJae Hyun Yoo */ 316b9122030SJae Hyun Yoo struct peci_wr_ia_msr_msg { 317b9122030SJae Hyun Yoo #define PECI_WRIAMSR_CMD 0xb5 318b9122030SJae Hyun Yoo 319b9122030SJae Hyun Yoo __u8 addr; 320b9122030SJae Hyun Yoo __u8 thread_id; 321b9122030SJae Hyun Yoo __u16 address; 322b9122030SJae Hyun Yoo __u8 tx_len; 323b9122030SJae Hyun Yoo __u8 cc; 324b9122030SJae Hyun Yoo __u8 padding[2]; 325b9122030SJae Hyun Yoo __u64 value; 326b9122030SJae Hyun Yoo } __attribute__((__packed__)); 327b9122030SJae Hyun Yoo 328b9122030SJae Hyun Yoo /** 329b9122030SJae Hyun Yoo * struct peci_rd_ia_msrex_msg - RdIAMSREX command 330b9122030SJae Hyun Yoo * @addr: address of the client 331b9122030SJae Hyun Yoo * @thread_id: ID of the specific logical processor 332b9122030SJae Hyun Yoo * @address: address of MSR to read from 333b9122030SJae Hyun Yoo * @cc: completion code 334b9122030SJae Hyun Yoo * @value: data to be read 335b9122030SJae Hyun Yoo * 336b9122030SJae Hyun Yoo * The RdIAMSREX() PECI command provides read access to Model Specific 337b9122030SJae Hyun Yoo * Registers (MSRs) defined in the processor's Intel Architecture (IA). 338b9122030SJae Hyun Yoo * The differences between RdIAMSREX() and RdIAMSR() are that: 339b9122030SJae Hyun Yoo * (1)RdIAMSR() can only read MC registers, RdIAMSREX() can read all MSRs 340b9122030SJae Hyun Yoo * (2)thread_id of RdIAMSR() is u8, thread_id of RdIAMSREX() is u16 341b9122030SJae Hyun Yoo */ 342b9122030SJae Hyun Yoo struct peci_rd_ia_msrex_msg { 343b9122030SJae Hyun Yoo #define PECI_RDIAMSREX_WRITE_LEN 6 344b9122030SJae Hyun Yoo #define PECI_RDIAMSREX_READ_LEN 9 345b9122030SJae Hyun Yoo #define PECI_RDIAMSREX_CMD 0xd1 346b9122030SJae Hyun Yoo 347b9122030SJae Hyun Yoo __u8 addr; 348b9122030SJae Hyun Yoo __u8 padding0; 349b9122030SJae Hyun Yoo __u16 thread_id; 350b9122030SJae Hyun Yoo __u16 address; 351b9122030SJae Hyun Yoo __u8 cc; 352b9122030SJae Hyun Yoo __u8 padding1; 353b9122030SJae Hyun Yoo __u64 value; 354b9122030SJae Hyun Yoo } __attribute__((__packed__)); 355b9122030SJae Hyun Yoo 356b9122030SJae Hyun Yoo /** 357b9122030SJae Hyun Yoo * struct peci_rd_pci_cfg_msg - RdPCIConfig command 358b9122030SJae Hyun Yoo * @addr: address of the client 359b9122030SJae Hyun Yoo * @bus: PCI bus number 360b9122030SJae Hyun Yoo * @device: PCI device number 361b9122030SJae Hyun Yoo * @function: specific function to read from 362b9122030SJae Hyun Yoo * @reg: specific register to read from 363b9122030SJae Hyun Yoo * @cc: completion code 364b9122030SJae Hyun Yoo * @pci_config: config data to be read 365b9122030SJae Hyun Yoo * 366b9122030SJae Hyun Yoo * The RdPCIConfig() command provides sideband read access to the PCI 367b9122030SJae Hyun Yoo * configuration space maintained in downstream devices external to the 368b9122030SJae Hyun Yoo * processor. 369b9122030SJae Hyun Yoo */ 370fb64f45dSJoel Stanley struct peci_rd_pci_cfg_msg { 371b9122030SJae Hyun Yoo #define PECI_RDPCICFG_WRITE_LEN 6 372b9122030SJae Hyun Yoo #define PECI_RDPCICFG_READ_LEN 5 373b9122030SJae Hyun Yoo #define PECI_RDPCICFG_READ_LEN_MAX 24 374b9122030SJae Hyun Yoo #define PECI_RDPCICFG_CMD 0x61 375b9122030SJae Hyun Yoo 376b9122030SJae Hyun Yoo __u8 addr; 377b9122030SJae Hyun Yoo __u8 bus; 378b9122030SJae Hyun Yoo #define PECI_PCI_BUS0_CPU0 0x00 379b9122030SJae Hyun Yoo #define PECI_PCI_BUS0_CPU1 0x80 380b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO_BUS 0x00 381b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO_DEV 0x08 382b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO_FUNC 0x02 383b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO 0xcc 384b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO_1 0xd0 385b9122030SJae Hyun Yoo #define PECI_PCI_CPUBUSNO_VALID 0xd4 386b9122030SJae Hyun Yoo 387b9122030SJae Hyun Yoo __u8 device; 388b9122030SJae Hyun Yoo __u8 function; 389b9122030SJae Hyun Yoo __u16 reg; 390b9122030SJae Hyun Yoo __u8 cc; 391b9122030SJae Hyun Yoo __u8 padding[1]; 392b9122030SJae Hyun Yoo __u8 pci_config[4]; 393b9122030SJae Hyun Yoo } __attribute__((__packed__)); 394b9122030SJae Hyun Yoo 395b9122030SJae Hyun Yoo /** 396b9122030SJae Hyun Yoo * struct peci_wr_pci_cfg_msg - WrPCIConfig command 397b9122030SJae Hyun Yoo * @addr: address of the client 398b9122030SJae Hyun Yoo * @bus: PCI bus number 399b9122030SJae Hyun Yoo * @device: PCI device number 400b9122030SJae Hyun Yoo * @function: specific function to write to 401b9122030SJae Hyun Yoo * @reg: specific register to write to 402b9122030SJae Hyun Yoo * @tx_len: number of data to be written in bytes 403b9122030SJae Hyun Yoo * @cc: completion code 404b9122030SJae Hyun Yoo * @pci_config: config data to be written 405b9122030SJae Hyun Yoo * 406b9122030SJae Hyun Yoo * The RdPCIConfig() command provides sideband write access to the PCI 407b9122030SJae Hyun Yoo * configuration space maintained in downstream devices external to the 408b9122030SJae Hyun Yoo * processor. 409b9122030SJae Hyun Yoo */ 410b9122030SJae Hyun Yoo struct peci_wr_pci_cfg_msg { 411b9122030SJae Hyun Yoo #define PECI_WRPCICFG_CMD 0x65 412b9122030SJae Hyun Yoo 413fb64f45dSJoel Stanley __u8 addr; 414fb64f45dSJoel Stanley __u8 bus; 415fb64f45dSJoel Stanley __u8 device; 416fb64f45dSJoel Stanley __u8 function; 417fb64f45dSJoel Stanley __u16 reg; 418b9122030SJae Hyun Yoo __u8 tx_len; 419b9122030SJae Hyun Yoo __u8 cc; 420fb64f45dSJoel Stanley __u8 pci_config[4]; 421fb64f45dSJoel Stanley } __attribute__((__packed__)); 422fb64f45dSJoel Stanley 423b9122030SJae Hyun Yoo /** 424b9122030SJae Hyun Yoo * struct peci_rd_pci_cfg_local_msg - RdPCIConfigLocal command 425b9122030SJae Hyun Yoo * @addr: address of the client 426b9122030SJae Hyun Yoo * @bus: PCI bus number 427b9122030SJae Hyun Yoo * @device: PCI device number 428b9122030SJae Hyun Yoo * @function: specific function to read from 429b9122030SJae Hyun Yoo * @reg: specific register to read from 430b9122030SJae Hyun Yoo * @rx_len: number of data to be read in bytes 431b9122030SJae Hyun Yoo * @cc: completion code 432b9122030SJae Hyun Yoo * @pci_config: config data to be read 433b9122030SJae Hyun Yoo * 434b9122030SJae Hyun Yoo * The RdPCIConfigLocal() command provides sideband read access to the PCI 435b9122030SJae Hyun Yoo * configuration space that resides within the processor. This includes all 436b9122030SJae Hyun Yoo * processor IIO and uncore registers within the PCI configuration space. 437b9122030SJae Hyun Yoo */ 438fb64f45dSJoel Stanley struct peci_rd_pci_cfg_local_msg { 439b9122030SJae Hyun Yoo #define PECI_RDPCICFGLOCAL_WRITE_LEN 5 440b9122030SJae Hyun Yoo #define PECI_RDPCICFGLOCAL_READ_LEN_BASE 1 441b9122030SJae Hyun Yoo #define PECI_RDPCICFGLOCAL_CMD 0xe1 442b9122030SJae Hyun Yoo 443fb64f45dSJoel Stanley __u8 addr; 444fb64f45dSJoel Stanley __u8 bus; 445fb64f45dSJoel Stanley __u8 device; 446fb64f45dSJoel Stanley __u8 function; 447fb64f45dSJoel Stanley __u16 reg; 448fb64f45dSJoel Stanley __u8 rx_len; 449b9122030SJae Hyun Yoo __u8 cc; 450fb64f45dSJoel Stanley __u8 pci_config[4]; 451fb64f45dSJoel Stanley } __attribute__((__packed__)); 452fb64f45dSJoel Stanley 453b9122030SJae Hyun Yoo /** 454b9122030SJae Hyun Yoo * struct peci_wr_pci_cfg_local_msg - WrPCIConfigLocal command 455b9122030SJae Hyun Yoo * @addr: address of the client 456b9122030SJae Hyun Yoo * @bus: PCI bus number 457b9122030SJae Hyun Yoo * @device: PCI device number 458b9122030SJae Hyun Yoo * @function: specific function to read from 459b9122030SJae Hyun Yoo * @reg: specific register to read from 460b9122030SJae Hyun Yoo * @tx_len: number of data to be written in bytes 461b9122030SJae Hyun Yoo * @cc: completion code 462b9122030SJae Hyun Yoo * @value: config data to be written 463b9122030SJae Hyun Yoo * 464b9122030SJae Hyun Yoo * The WrPCIConfigLocal() command provides sideband write access to the PCI 465b9122030SJae Hyun Yoo * configuration space that resides within the processor. PECI originators can 466b9122030SJae Hyun Yoo * access this space even before BIOS enumeration of the system buses. 467b9122030SJae Hyun Yoo */ 468fb64f45dSJoel Stanley struct peci_wr_pci_cfg_local_msg { 469b9122030SJae Hyun Yoo #define PECI_WRPCICFGLOCAL_WRITE_LEN_BASE 6 470b9122030SJae Hyun Yoo #define PECI_WRPCICFGLOCAL_READ_LEN 1 471b9122030SJae Hyun Yoo #define PECI_WRPCICFGLOCAL_CMD 0xe5 472b9122030SJae Hyun Yoo 473fb64f45dSJoel Stanley __u8 addr; 474fb64f45dSJoel Stanley __u8 bus; 475fb64f45dSJoel Stanley __u8 device; 476fb64f45dSJoel Stanley __u8 function; 477fb64f45dSJoel Stanley __u16 reg; 478fb64f45dSJoel Stanley __u8 tx_len; 479b9122030SJae Hyun Yoo __u8 cc; 480fb64f45dSJoel Stanley __u32 value; 481fb64f45dSJoel Stanley } __attribute__((__packed__)); 482fb64f45dSJoel Stanley 483b9122030SJae Hyun Yoo struct peci_rd_end_pt_cfg_msg { 484b9122030SJae Hyun Yoo #define PECI_RDENDPTCFG_PCI_WRITE_LEN 12 485b9122030SJae Hyun Yoo #define PECI_RDENDPTCFG_MMIO_D_WRITE_LEN 14 486b9122030SJae Hyun Yoo #define PECI_RDENDPTCFG_MMIO_Q_WRITE_LEN 18 487b9122030SJae Hyun Yoo #define PECI_RDENDPTCFG_READ_LEN_BASE 1 488b9122030SJae Hyun Yoo #define PECI_RDENDPTCFG_CMD 0xc1 489b9122030SJae Hyun Yoo 490b9122030SJae Hyun Yoo __u8 addr; 491b9122030SJae Hyun Yoo __u8 msg_type; 492b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_TYPE_LOCAL_PCI 0x03 493b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_TYPE_PCI 0x04 494b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_TYPE_MMIO 0x05 495b9122030SJae Hyun Yoo 496b9122030SJae Hyun Yoo union { 497b9122030SJae Hyun Yoo struct { 498b9122030SJae Hyun Yoo __u8 seg; 499b9122030SJae Hyun Yoo __u8 bus; 500b9122030SJae Hyun Yoo __u8 device; 501b9122030SJae Hyun Yoo __u8 function; 502b9122030SJae Hyun Yoo __u16 reg; 503b9122030SJae Hyun Yoo } pci_cfg; 504b9122030SJae Hyun Yoo struct { 505b9122030SJae Hyun Yoo __u8 seg; 506b9122030SJae Hyun Yoo __u8 bus; 507b9122030SJae Hyun Yoo __u8 device; 508b9122030SJae Hyun Yoo __u8 function; 509b9122030SJae Hyun Yoo __u8 bar; 510b9122030SJae Hyun Yoo __u8 addr_type; 511b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_ADDR_TYPE_PCI 0x04 512b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_D 0x05 513b9122030SJae Hyun Yoo #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_Q 0x06 514b9122030SJae Hyun Yoo 515b9122030SJae Hyun Yoo __u64 offset; 516b9122030SJae Hyun Yoo } mmio; 517b9122030SJae Hyun Yoo } params; 518b9122030SJae Hyun Yoo __u8 rx_len; 519b9122030SJae Hyun Yoo __u8 cc; 520b9122030SJae Hyun Yoo __u8 padding[2]; 521b9122030SJae Hyun Yoo __u8 data[8]; 522b9122030SJae Hyun Yoo } __attribute__((__packed__)); 523b9122030SJae Hyun Yoo 524b9122030SJae Hyun Yoo struct peci_wr_end_pt_cfg_msg { 525b9122030SJae Hyun Yoo #define PECI_WRENDPTCFG_PCI_WRITE_LEN_BASE 13 526b9122030SJae Hyun Yoo #define PECI_WRENDPTCFG_MMIO_D_WRITE_LEN_BASE 15 527b9122030SJae Hyun Yoo #define PECI_WRENDPTCFG_MMIO_Q_WRITE_LEN_BASE 19 528b9122030SJae Hyun Yoo #define PECI_WRENDPTCFG_READ_LEN 1 529b9122030SJae Hyun Yoo #define PECI_WRENDPTCFG_CMD 0xc5 530b9122030SJae Hyun Yoo 531b9122030SJae Hyun Yoo __u8 addr; 532b9122030SJae Hyun Yoo __u8 msg_type; 533b9122030SJae Hyun Yoo /* See msg_type in struct peci_rd_end_pt_cfg_msg */ 534b9122030SJae Hyun Yoo 535b9122030SJae Hyun Yoo union { 536b9122030SJae Hyun Yoo struct { 537b9122030SJae Hyun Yoo __u8 seg; 538b9122030SJae Hyun Yoo __u8 bus; 539b9122030SJae Hyun Yoo __u8 device; 540b9122030SJae Hyun Yoo __u8 function; 541b9122030SJae Hyun Yoo __u16 reg; 542b9122030SJae Hyun Yoo } pci_cfg; 543b9122030SJae Hyun Yoo struct { 544b9122030SJae Hyun Yoo __u8 seg; 545b9122030SJae Hyun Yoo __u8 bus; 546b9122030SJae Hyun Yoo __u8 device; 547b9122030SJae Hyun Yoo __u8 function; 548b9122030SJae Hyun Yoo __u8 bar; 549b9122030SJae Hyun Yoo __u8 addr_type; 550b9122030SJae Hyun Yoo /* See addr_type in struct peci_rd_end_pt_cfg_msg */ 551b9122030SJae Hyun Yoo 552b9122030SJae Hyun Yoo __u64 offset; 553b9122030SJae Hyun Yoo } mmio; 554b9122030SJae Hyun Yoo } params; 555b9122030SJae Hyun Yoo __u8 tx_len; 556b9122030SJae Hyun Yoo __u8 cc; 557b9122030SJae Hyun Yoo __u8 padding[2]; 558b9122030SJae Hyun Yoo __u64 value; 559b9122030SJae Hyun Yoo } __attribute__((__packed__)); 560b9122030SJae Hyun Yoo 561b9122030SJae Hyun Yoo /* Crashdump Agent */ 562b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_CORE 0x00 563b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_TOR 0x01 564b9122030SJae Hyun Yoo 565b9122030SJae Hyun Yoo /* Crashdump Agent Param */ 566b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_PAYLOAD_SIZE 0x00 567b9122030SJae Hyun Yoo 568b9122030SJae Hyun Yoo /* Crashdump Agent Data Param */ 569b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_AGENT_ID 0x00 570b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_AGENT_PARAM 0x01 571b9122030SJae Hyun Yoo 572fb64f45dSJoel Stanley struct peci_crashdump_disc_msg { 573fb64f45dSJoel Stanley __u8 addr; 574fb64f45dSJoel Stanley __u8 subopcode; 575b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_ENABLED 0x00 576b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_NUM_AGENTS 0x01 577b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_AGENT_DATA 0x02 578b9122030SJae Hyun Yoo 579b9122030SJae Hyun Yoo __u8 cc; 580fb64f45dSJoel Stanley __u8 param0; 581fb64f45dSJoel Stanley __u16 param1; 582fb64f45dSJoel Stanley __u8 param2; 583fb64f45dSJoel Stanley __u8 rx_len; 584fb64f45dSJoel Stanley __u8 data[8]; 585fb64f45dSJoel Stanley } __attribute__((__packed__)); 586fb64f45dSJoel Stanley 587fb64f45dSJoel Stanley struct peci_crashdump_get_frame_msg { 588b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_DISC_WRITE_LEN 9 589b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_DISC_READ_LEN_BASE 1 590b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_DISC_VERSION 0 591b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_DISC_OPCODE 1 592b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_GET_FRAME_WRITE_LEN 10 593b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_GET_FRAME_READ_LEN_BASE 1 594b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_GET_FRAME_VERSION 0 595b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_GET_FRAME_OPCODE 3 596b9122030SJae Hyun Yoo #define PECI_CRASHDUMP_CMD 0x71 597b9122030SJae Hyun Yoo 598fb64f45dSJoel Stanley __u8 addr; 599b9122030SJae Hyun Yoo __u8 padding0; 600fb64f45dSJoel Stanley __u16 param0; 601fb64f45dSJoel Stanley __u16 param1; 602fb64f45dSJoel Stanley __u16 param2; 603fb64f45dSJoel Stanley __u8 rx_len; 604b9122030SJae Hyun Yoo __u8 cc; 605b9122030SJae Hyun Yoo __u8 padding1[2]; 606fb64f45dSJoel Stanley __u8 data[16]; 607fb64f45dSJoel Stanley } __attribute__((__packed__)); 608fb64f45dSJoel Stanley 609b9122030SJae Hyun Yoo #define PECI_IOC_BASE 0xb7 610b9122030SJae Hyun Yoo 611b9122030SJae Hyun Yoo #define PECI_IOC_XFER \ 612b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_XFER, struct peci_xfer_msg) 613fb64f45dSJoel Stanley 614fb64f45dSJoel Stanley #define PECI_IOC_PING \ 615fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_PING, struct peci_ping_msg) 616fb64f45dSJoel Stanley 617fb64f45dSJoel Stanley #define PECI_IOC_GET_DIB \ 618fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_GET_DIB, struct peci_get_dib_msg) 619fb64f45dSJoel Stanley 620fb64f45dSJoel Stanley #define PECI_IOC_GET_TEMP \ 621fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_GET_TEMP, struct peci_get_temp_msg) 622fb64f45dSJoel Stanley 623fb64f45dSJoel Stanley #define PECI_IOC_RD_PKG_CFG \ 624fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PKG_CFG, struct peci_rd_pkg_cfg_msg) 625fb64f45dSJoel Stanley 626fb64f45dSJoel Stanley #define PECI_IOC_WR_PKG_CFG \ 627fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PKG_CFG, struct peci_wr_pkg_cfg_msg) 628fb64f45dSJoel Stanley 629fb64f45dSJoel Stanley #define PECI_IOC_RD_IA_MSR \ 630fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSR, struct peci_rd_ia_msr_msg) 631fb64f45dSJoel Stanley 632b9122030SJae Hyun Yoo #define PECI_IOC_WR_IA_MSR \ 633b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_WR_IA_MSR, struct peci_wr_ia_msr_msg) 634b9122030SJae Hyun Yoo 635b9122030SJae Hyun Yoo #define PECI_IOC_RD_IA_MSREX \ 636b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSREX, struct peci_rd_ia_msrex_msg) 637b9122030SJae Hyun Yoo 638fb64f45dSJoel Stanley #define PECI_IOC_RD_PCI_CFG \ 639fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG, struct peci_rd_pci_cfg_msg) 640fb64f45dSJoel Stanley 641b9122030SJae Hyun Yoo #define PECI_IOC_WR_PCI_CFG \ 642b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG, struct peci_wr_pci_cfg_msg) 643b9122030SJae Hyun Yoo 644fb64f45dSJoel Stanley #define PECI_IOC_RD_PCI_CFG_LOCAL \ 645fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG_LOCAL, \ 646fb64f45dSJoel Stanley struct peci_rd_pci_cfg_local_msg) 647fb64f45dSJoel Stanley 648fb64f45dSJoel Stanley #define PECI_IOC_WR_PCI_CFG_LOCAL \ 649fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG_LOCAL, \ 650fb64f45dSJoel Stanley struct peci_wr_pci_cfg_local_msg) 651fb64f45dSJoel Stanley 652b9122030SJae Hyun Yoo #define PECI_IOC_RD_END_PT_CFG \ 653b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_RD_END_PT_CFG, \ 654b9122030SJae Hyun Yoo struct peci_rd_end_pt_cfg_msg) 655b9122030SJae Hyun Yoo 656b9122030SJae Hyun Yoo #define PECI_IOC_WR_END_PT_CFG \ 657b9122030SJae Hyun Yoo _IOWR(PECI_IOC_BASE, PECI_CMD_WR_END_PT_CFG, \ 658b9122030SJae Hyun Yoo struct peci_wr_end_pt_cfg_msg) 659b9122030SJae Hyun Yoo 660fb64f45dSJoel Stanley #define PECI_IOC_CRASHDUMP_DISC \ 661fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_DISC, \ 662fb64f45dSJoel Stanley struct peci_crashdump_disc_msg) 663fb64f45dSJoel Stanley 664fb64f45dSJoel Stanley #define PECI_IOC_CRASHDUMP_GET_FRAME \ 665fb64f45dSJoel Stanley _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_GET_FRAME, \ 666fb64f45dSJoel Stanley struct peci_crashdump_get_frame_msg) 667fb64f45dSJoel Stanley 668ec77caa4SEd Tanous #ifdef __cplusplus 669ec77caa4SEd Tanous } 670ec77caa4SEd Tanous #endif 671ec77caa4SEd Tanous 672fb64f45dSJoel Stanley #endif /* __PECI_IOCTL_H */ 673*d02ad49eSPatrick Williams 674*d02ad49eSPatrick Williams // NOLINTEND 675fb64f45dSJoel Stanley // clang-format on 676