1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2a47a12beSStefan Roese /*
3a47a12beSStefan Roese * (C) Copyright 2002
4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5a47a12beSStefan Roese */
6a47a12beSStefan Roese
7a47a12beSStefan Roese #include <common.h>
8a47a12beSStefan Roese
9a47a12beSStefan Roese /*
10a47a12beSStefan Roese * CPU test
11a47a12beSStefan Roese * Ternary instructions instr rA,rS,UIMM
12a47a12beSStefan Roese *
13a47a12beSStefan Roese * Logic instructions: ori, oris, xori, xoris
14a47a12beSStefan Roese *
15a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and
16a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use
17a47a12beSStefan Roese * different sets of operand registers and result registers.
18a47a12beSStefan Roese */
19a47a12beSStefan Roese
20a47a12beSStefan Roese #include <post.h>
21a47a12beSStefan Roese #include "cpu_asm.h"
22a47a12beSStefan Roese
23a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU
24a47a12beSStefan Roese
25a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
26a47a12beSStefan Roese extern ulong cpu_post_makecr (long v);
27a47a12beSStefan Roese
28a47a12beSStefan Roese static struct cpu_post_threei_s
29a47a12beSStefan Roese {
30a47a12beSStefan Roese ulong cmd;
31a47a12beSStefan Roese ulong op1;
32a47a12beSStefan Roese ushort op2;
33a47a12beSStefan Roese ulong res;
34a47a12beSStefan Roese } cpu_post_threei_table[] =
35a47a12beSStefan Roese {
36a47a12beSStefan Roese {
37a47a12beSStefan Roese OP_ORI,
38a47a12beSStefan Roese 0x80000000,
39a47a12beSStefan Roese 0xffff,
40a47a12beSStefan Roese 0x8000ffff
41a47a12beSStefan Roese },
42a47a12beSStefan Roese {
43a47a12beSStefan Roese OP_ORIS,
44a47a12beSStefan Roese 0x00008000,
45a47a12beSStefan Roese 0xffff,
46a47a12beSStefan Roese 0xffff8000
47a47a12beSStefan Roese },
48a47a12beSStefan Roese {
49a47a12beSStefan Roese OP_XORI,
50a47a12beSStefan Roese 0x8000ffff,
51a47a12beSStefan Roese 0xffff,
52a47a12beSStefan Roese 0x80000000
53a47a12beSStefan Roese },
54a47a12beSStefan Roese {
55a47a12beSStefan Roese OP_XORIS,
56a47a12beSStefan Roese 0x00008000,
57a47a12beSStefan Roese 0xffff,
58a47a12beSStefan Roese 0xffff8000
59a47a12beSStefan Roese },
60a47a12beSStefan Roese };
61d2397817SMike Frysinger static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
62a47a12beSStefan Roese
cpu_post_test_threei(void)63a47a12beSStefan Roese int cpu_post_test_threei (void)
64a47a12beSStefan Roese {
65a47a12beSStefan Roese int ret = 0;
66a47a12beSStefan Roese unsigned int i, reg;
67a47a12beSStefan Roese int flag = disable_interrupts();
68a47a12beSStefan Roese
69a47a12beSStefan Roese for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
70a47a12beSStefan Roese {
71a47a12beSStefan Roese struct cpu_post_threei_s *test = cpu_post_threei_table + i;
72a47a12beSStefan Roese
73a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++)
74a47a12beSStefan Roese {
75a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32;
76a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32;
77a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15;
78a47a12beSStefan Roese unsigned long code[] =
79a47a12beSStefan Roese {
80a47a12beSStefan Roese ASM_STW(stk, 1, -4),
81a47a12beSStefan Roese ASM_ADDI(stk, 1, -16),
82a47a12beSStefan Roese ASM_STW(3, stk, 8),
83a47a12beSStefan Roese ASM_STW(reg0, stk, 4),
84a47a12beSStefan Roese ASM_STW(reg1, stk, 0),
85a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8),
86a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2),
87a47a12beSStefan Roese ASM_STW(reg1, stk, 8),
88a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0),
89a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4),
90a47a12beSStefan Roese ASM_LWZ(3, stk, 8),
91a47a12beSStefan Roese ASM_ADDI(1, stk, 16),
92a47a12beSStefan Roese ASM_LWZ(stk, 1, -4),
93a47a12beSStefan Roese ASM_BLR,
94a47a12beSStefan Roese };
95a47a12beSStefan Roese ulong res;
96a47a12beSStefan Roese ulong cr;
97a47a12beSStefan Roese
98a47a12beSStefan Roese cr = 0;
99a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1);
100a47a12beSStefan Roese
101a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1;
102a47a12beSStefan Roese
103a47a12beSStefan Roese if (ret != 0)
104a47a12beSStefan Roese {
105a47a12beSStefan Roese post_log ("Error at threei test %d !\n", i);
106a47a12beSStefan Roese }
107a47a12beSStefan Roese }
108a47a12beSStefan Roese }
109a47a12beSStefan Roese
110a47a12beSStefan Roese if (flag)
111a47a12beSStefan Roese enable_interrupts();
112a47a12beSStefan Roese
113a47a12beSStefan Roese return ret;
114a47a12beSStefan Roese }
115a47a12beSStefan Roese
116a47a12beSStefan Roese #endif
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