1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * 29*a47a12beSStefan Roese * This test checks the arithmetic logic unit (ALU) of CPU. 30*a47a12beSStefan Roese * It tests independently various groups of instructions using 31*a47a12beSStefan Roese * run-time modification of the code to reduce the memory footprint. 32*a47a12beSStefan Roese * For more details refer to post/cpu/ *.c files. 33*a47a12beSStefan Roese */ 34*a47a12beSStefan Roese 35*a47a12beSStefan Roese #include <watchdog.h> 36*a47a12beSStefan Roese #include <post.h> 37*a47a12beSStefan Roese #include <asm/mmu.h> 38*a47a12beSStefan Roese 39*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 40*a47a12beSStefan Roese 41*a47a12beSStefan Roese extern int cpu_post_test_cmp (void); 42*a47a12beSStefan Roese extern int cpu_post_test_cmpi (void); 43*a47a12beSStefan Roese extern int cpu_post_test_two (void); 44*a47a12beSStefan Roese extern int cpu_post_test_twox (void); 45*a47a12beSStefan Roese extern int cpu_post_test_three (void); 46*a47a12beSStefan Roese extern int cpu_post_test_threex (void); 47*a47a12beSStefan Roese extern int cpu_post_test_threei (void); 48*a47a12beSStefan Roese extern int cpu_post_test_andi (void); 49*a47a12beSStefan Roese extern int cpu_post_test_srawi (void); 50*a47a12beSStefan Roese extern int cpu_post_test_rlwnm (void); 51*a47a12beSStefan Roese extern int cpu_post_test_rlwinm (void); 52*a47a12beSStefan Roese extern int cpu_post_test_rlwimi (void); 53*a47a12beSStefan Roese extern int cpu_post_test_store (void); 54*a47a12beSStefan Roese extern int cpu_post_test_load (void); 55*a47a12beSStefan Roese extern int cpu_post_test_cr (void); 56*a47a12beSStefan Roese extern int cpu_post_test_b (void); 57*a47a12beSStefan Roese extern int cpu_post_test_multi (void); 58*a47a12beSStefan Roese extern int cpu_post_test_string (void); 59*a47a12beSStefan Roese extern int cpu_post_test_complex (void); 60*a47a12beSStefan Roese 61*a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 62*a47a12beSStefan Roese 63*a47a12beSStefan Roese ulong cpu_post_makecr (long v) 64*a47a12beSStefan Roese { 65*a47a12beSStefan Roese ulong cr = 0; 66*a47a12beSStefan Roese 67*a47a12beSStefan Roese if (v < 0) 68*a47a12beSStefan Roese cr |= 0x80000000; 69*a47a12beSStefan Roese if (v > 0) 70*a47a12beSStefan Roese cr |= 0x40000000; 71*a47a12beSStefan Roese if (v == 0) 72*a47a12beSStefan Roese cr |= 0x20000000; 73*a47a12beSStefan Roese 74*a47a12beSStefan Roese return cr; 75*a47a12beSStefan Roese } 76*a47a12beSStefan Roese 77*a47a12beSStefan Roese int cpu_post_test (int flags) 78*a47a12beSStefan Roese { 79*a47a12beSStefan Roese int ic = icache_status (); 80*a47a12beSStefan Roese int ret = 0; 81*a47a12beSStefan Roese 82*a47a12beSStefan Roese WATCHDOG_RESET(); 83*a47a12beSStefan Roese if (ic) 84*a47a12beSStefan Roese icache_disable (); 85*a47a12beSStefan Roese #ifdef CONFIG_4xx_DCACHE 86*a47a12beSStefan Roese /* disable cache */ 87*a47a12beSStefan Roese change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); 88*a47a12beSStefan Roese #endif 89*a47a12beSStefan Roese 90*a47a12beSStefan Roese if (ret == 0) 91*a47a12beSStefan Roese ret = cpu_post_test_cmp (); 92*a47a12beSStefan Roese if (ret == 0) 93*a47a12beSStefan Roese ret = cpu_post_test_cmpi (); 94*a47a12beSStefan Roese if (ret == 0) 95*a47a12beSStefan Roese ret = cpu_post_test_two (); 96*a47a12beSStefan Roese if (ret == 0) 97*a47a12beSStefan Roese ret = cpu_post_test_twox (); 98*a47a12beSStefan Roese WATCHDOG_RESET(); 99*a47a12beSStefan Roese if (ret == 0) 100*a47a12beSStefan Roese ret = cpu_post_test_three (); 101*a47a12beSStefan Roese if (ret == 0) 102*a47a12beSStefan Roese ret = cpu_post_test_threex (); 103*a47a12beSStefan Roese if (ret == 0) 104*a47a12beSStefan Roese ret = cpu_post_test_threei (); 105*a47a12beSStefan Roese if (ret == 0) 106*a47a12beSStefan Roese ret = cpu_post_test_andi (); 107*a47a12beSStefan Roese WATCHDOG_RESET(); 108*a47a12beSStefan Roese if (ret == 0) 109*a47a12beSStefan Roese ret = cpu_post_test_srawi (); 110*a47a12beSStefan Roese if (ret == 0) 111*a47a12beSStefan Roese ret = cpu_post_test_rlwnm (); 112*a47a12beSStefan Roese if (ret == 0) 113*a47a12beSStefan Roese ret = cpu_post_test_rlwinm (); 114*a47a12beSStefan Roese if (ret == 0) 115*a47a12beSStefan Roese ret = cpu_post_test_rlwimi (); 116*a47a12beSStefan Roese WATCHDOG_RESET(); 117*a47a12beSStefan Roese if (ret == 0) 118*a47a12beSStefan Roese ret = cpu_post_test_store (); 119*a47a12beSStefan Roese if (ret == 0) 120*a47a12beSStefan Roese ret = cpu_post_test_load (); 121*a47a12beSStefan Roese if (ret == 0) 122*a47a12beSStefan Roese ret = cpu_post_test_cr (); 123*a47a12beSStefan Roese if (ret == 0) 124*a47a12beSStefan Roese ret = cpu_post_test_b (); 125*a47a12beSStefan Roese WATCHDOG_RESET(); 126*a47a12beSStefan Roese if (ret == 0) 127*a47a12beSStefan Roese ret = cpu_post_test_multi (); 128*a47a12beSStefan Roese WATCHDOG_RESET(); 129*a47a12beSStefan Roese if (ret == 0) 130*a47a12beSStefan Roese ret = cpu_post_test_string (); 131*a47a12beSStefan Roese if (ret == 0) 132*a47a12beSStefan Roese ret = cpu_post_test_complex (); 133*a47a12beSStefan Roese WATCHDOG_RESET(); 134*a47a12beSStefan Roese 135*a47a12beSStefan Roese if (ic) 136*a47a12beSStefan Roese icache_enable (); 137*a47a12beSStefan Roese #ifdef CONFIG_4xx_DCACHE 138*a47a12beSStefan Roese /* enable cache */ 139*a47a12beSStefan Roese change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); 140*a47a12beSStefan Roese #endif 141*a47a12beSStefan Roese 142*a47a12beSStefan Roese WATCHDOG_RESET(); 143*a47a12beSStefan Roese 144*a47a12beSStefan Roese return ret; 145*a47a12beSStefan Roese } 146*a47a12beSStefan Roese 147*a47a12beSStefan Roese #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ 148