1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese/* 3a47a12beSStefan Roese * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> 4a47a12beSStefan Roese */ 5a47a12beSStefan Roese 6a47a12beSStefan Roese#include <config.h> 7a47a12beSStefan Roese 8a47a12beSStefan Roese#include <post.h> 9a47a12beSStefan Roese#include <ppc_asm.tmpl> 10a47a12beSStefan Roese#include <ppc_defs.h> 11a47a12beSStefan Roese#include <asm/cache.h> 12a47a12beSStefan Roese 13a47a12beSStefan Roese#if CONFIG_POST & CONFIG_SYS_POST_CPU 14a47a12beSStefan Roese 15a47a12beSStefan Roese/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ 16a47a12beSStefan Roese .global cpu_post_exec_02 17a47a12beSStefan Roesecpu_post_exec_02: 18a47a12beSStefan Roese isync 19a47a12beSStefan Roese mflr r0 20a47a12beSStefan Roese stwu r0, -4(r1) 21a47a12beSStefan Roese 22a47a12beSStefan Roese subi r1, r1, 104 23a47a12beSStefan Roese stmw r6, 0(r1) 24a47a12beSStefan Roese 25a47a12beSStefan Roese mtlr r3 26a47a12beSStefan Roese mr r3, r4 27a47a12beSStefan Roese mr r4, r5 28a47a12beSStefan Roese blrl 29a47a12beSStefan Roese 30a47a12beSStefan Roese lmw r6, 0(r1) 31a47a12beSStefan Roese addi r1, r1, 104 32a47a12beSStefan Roese 33a47a12beSStefan Roese lwz r0, 0(r1) 34a47a12beSStefan Roese addi r1, r1, 4 35a47a12beSStefan Roese mtlr r0 36a47a12beSStefan Roese blr 37a47a12beSStefan Roese 38a47a12beSStefan Roese/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ 39a47a12beSStefan Roese .global cpu_post_exec_04 40a47a12beSStefan Roesecpu_post_exec_04: 41a47a12beSStefan Roese isync 42a47a12beSStefan Roese mflr r0 43a47a12beSStefan Roese stwu r0, -4(r1) 44a47a12beSStefan Roese 45a47a12beSStefan Roese subi r1, r1, 96 46a47a12beSStefan Roese stmw r8, 0(r1) 47a47a12beSStefan Roese 48a47a12beSStefan Roese mtlr r3 49a47a12beSStefan Roese mr r3, r4 50a47a12beSStefan Roese mr r4, r5 51a47a12beSStefan Roese mr r5, r6 52a47a12beSStefan Roese mtxer r7 53a47a12beSStefan Roese blrl 54a47a12beSStefan Roese 55a47a12beSStefan Roese lmw r8, 0(r1) 56a47a12beSStefan Roese addi r1, r1, 96 57a47a12beSStefan Roese 58a47a12beSStefan Roese lwz r0, 0(r1) 59a47a12beSStefan Roese addi r1, r1, 4 60a47a12beSStefan Roese mtlr r0 61a47a12beSStefan Roese blr 62a47a12beSStefan Roese 63a47a12beSStefan Roese/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ 64a47a12beSStefan Roese .global cpu_post_exec_12 65a47a12beSStefan Roesecpu_post_exec_12: 66a47a12beSStefan Roese isync 67a47a12beSStefan Roese mflr r0 68a47a12beSStefan Roese stwu r0, -4(r1) 69a47a12beSStefan Roese stwu r4, -4(r1) 70a47a12beSStefan Roese 71a47a12beSStefan Roese mtlr r3 72a47a12beSStefan Roese mr r3, r5 73a47a12beSStefan Roese mr r4, r6 74a47a12beSStefan Roese blrl 75a47a12beSStefan Roese 76a47a12beSStefan Roese lwz r4, 0(r1) 77a47a12beSStefan Roese stw r3, 0(r4) 78a47a12beSStefan Roese 79a47a12beSStefan Roese lwz r0, 4(r1) 80a47a12beSStefan Roese addi r1, r1, 8 81a47a12beSStefan Roese mtlr r0 82a47a12beSStefan Roese blr 83a47a12beSStefan Roese 84a47a12beSStefan Roese/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ 85a47a12beSStefan Roese .global cpu_post_exec_11 86a47a12beSStefan Roesecpu_post_exec_11: 87a47a12beSStefan Roese isync 88a47a12beSStefan Roese mflr r0 89a47a12beSStefan Roese stwu r0, -4(r1) 90a47a12beSStefan Roese stwu r4, -4(r1) 91a47a12beSStefan Roese 92a47a12beSStefan Roese mtlr r3 93a47a12beSStefan Roese mr r3, r5 94a47a12beSStefan Roese blrl 95a47a12beSStefan Roese 96a47a12beSStefan Roese lwz r4, 0(r1) 97a47a12beSStefan Roese stw r3, 0(r4) 98a47a12beSStefan Roese 99a47a12beSStefan Roese lwz r0, 4(r1) 100a47a12beSStefan Roese addi r1, r1, 8 101a47a12beSStefan Roese mtlr r0 102a47a12beSStefan Roese blr 103a47a12beSStefan Roese 104a47a12beSStefan Roese/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ 105a47a12beSStefan Roese .global cpu_post_exec_21 106a47a12beSStefan Roesecpu_post_exec_21: 107a47a12beSStefan Roese isync 108a47a12beSStefan Roese mflr r0 109a47a12beSStefan Roese stwu r0, -4(r1) 110a47a12beSStefan Roese stwu r4, -4(r1) 111a47a12beSStefan Roese stwu r5, -4(r1) 112a47a12beSStefan Roese 113a47a12beSStefan Roese li r0, 0 114a47a12beSStefan Roese mtxer r0 115a47a12beSStefan Roese lwz r0, 0(r4) 116a47a12beSStefan Roese mtcr r0 117a47a12beSStefan Roese 118a47a12beSStefan Roese mtlr r3 119a47a12beSStefan Roese mr r3, r6 120a47a12beSStefan Roese blrl 121a47a12beSStefan Roese 122a47a12beSStefan Roese mfcr r0 123a47a12beSStefan Roese lwz r4, 4(r1) 124a47a12beSStefan Roese stw r0, 0(r4) 125a47a12beSStefan Roese lwz r4, 0(r1) 126a47a12beSStefan Roese stw r3, 0(r4) 127a47a12beSStefan Roese 128a47a12beSStefan Roese lwz r0, 8(r1) 129a47a12beSStefan Roese addi r1, r1, 12 130a47a12beSStefan Roese mtlr r0 131a47a12beSStefan Roese blr 132a47a12beSStefan Roese 133a47a12beSStefan Roese/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 134a47a12beSStefan Roese ulong op2); */ 135a47a12beSStefan Roese .global cpu_post_exec_22 136a47a12beSStefan Roesecpu_post_exec_22: 137a47a12beSStefan Roese isync 138a47a12beSStefan Roese mflr r0 139a47a12beSStefan Roese stwu r0, -4(r1) 140a47a12beSStefan Roese stwu r4, -4(r1) 141a47a12beSStefan Roese stwu r5, -4(r1) 142a47a12beSStefan Roese 143a47a12beSStefan Roese li r0, 0 144a47a12beSStefan Roese mtxer r0 145a47a12beSStefan Roese lwz r0, 0(r4) 146a47a12beSStefan Roese mtcr r0 147a47a12beSStefan Roese 148a47a12beSStefan Roese mtlr r3 149a47a12beSStefan Roese mr r3, r6 150a47a12beSStefan Roese mr r4, r7 151a47a12beSStefan Roese blrl 152a47a12beSStefan Roese 153a47a12beSStefan Roese mfcr r0 154a47a12beSStefan Roese lwz r4, 4(r1) 155a47a12beSStefan Roese stw r0, 0(r4) 156a47a12beSStefan Roese lwz r4, 0(r1) 157a47a12beSStefan Roese stw r3, 0(r4) 158a47a12beSStefan Roese 159a47a12beSStefan Roese lwz r0, 8(r1) 160a47a12beSStefan Roese addi r1, r1, 12 161a47a12beSStefan Roese mtlr r0 162a47a12beSStefan Roese blr 163a47a12beSStefan Roese 164a47a12beSStefan Roese/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ 165a47a12beSStefan Roese .global cpu_post_exec_12w 166a47a12beSStefan Roesecpu_post_exec_12w: 167a47a12beSStefan Roese isync 168a47a12beSStefan Roese mflr r0 169a47a12beSStefan Roese stwu r0, -4(r1) 170a47a12beSStefan Roese stwu r4, -4(r1) 171a47a12beSStefan Roese 172a47a12beSStefan Roese mtlr r3 173a47a12beSStefan Roese lwz r3, 0(r4) 174a47a12beSStefan Roese mr r4, r5 175a47a12beSStefan Roese mr r5, r6 176a47a12beSStefan Roese blrl 177a47a12beSStefan Roese 178a47a12beSStefan Roese lwz r4, 0(r1) 179a47a12beSStefan Roese stw r3, 0(r4) 180a47a12beSStefan Roese 181a47a12beSStefan Roese lwz r0, 4(r1) 182a47a12beSStefan Roese addi r1, r1, 8 183a47a12beSStefan Roese mtlr r0 184a47a12beSStefan Roese blr 185a47a12beSStefan Roese 186a47a12beSStefan Roese/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ 187a47a12beSStefan Roese .global cpu_post_exec_11w 188a47a12beSStefan Roesecpu_post_exec_11w: 189a47a12beSStefan Roese isync 190a47a12beSStefan Roese mflr r0 191a47a12beSStefan Roese stwu r0, -4(r1) 192a47a12beSStefan Roese stwu r4, -4(r1) 193a47a12beSStefan Roese 194a47a12beSStefan Roese mtlr r3 195a47a12beSStefan Roese lwz r3, 0(r4) 196a47a12beSStefan Roese mr r4, r5 197a47a12beSStefan Roese blrl 198a47a12beSStefan Roese 199a47a12beSStefan Roese lwz r4, 0(r1) 200a47a12beSStefan Roese stw r3, 0(r4) 201a47a12beSStefan Roese 202a47a12beSStefan Roese lwz r0, 4(r1) 203a47a12beSStefan Roese addi r1, r1, 8 204a47a12beSStefan Roese mtlr r0 205a47a12beSStefan Roese blr 206a47a12beSStefan Roese 207a47a12beSStefan Roese/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ 208a47a12beSStefan Roese .global cpu_post_exec_22w 209a47a12beSStefan Roesecpu_post_exec_22w: 210a47a12beSStefan Roese isync 211a47a12beSStefan Roese mflr r0 212a47a12beSStefan Roese stwu r0, -4(r1) 213a47a12beSStefan Roese stwu r4, -4(r1) 214a47a12beSStefan Roese stwu r6, -4(r1) 215a47a12beSStefan Roese 216a47a12beSStefan Roese mtlr r3 217a47a12beSStefan Roese lwz r3, 0(r4) 218a47a12beSStefan Roese mr r4, r5 219a47a12beSStefan Roese blrl 220a47a12beSStefan Roese 221a47a12beSStefan Roese lwz r4, 4(r1) 222a47a12beSStefan Roese stw r3, 0(r4) 223a47a12beSStefan Roese lwz r4, 0(r1) 224a47a12beSStefan Roese stw r5, 0(r4) 225a47a12beSStefan Roese 226a47a12beSStefan Roese lwz r0, 8(r1) 227a47a12beSStefan Roese addi r1, r1, 12 228a47a12beSStefan Roese mtlr r0 229a47a12beSStefan Roese blr 230a47a12beSStefan Roese 231a47a12beSStefan Roese/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ 232a47a12beSStefan Roese .global cpu_post_exec_21w 233a47a12beSStefan Roesecpu_post_exec_21w: 234a47a12beSStefan Roese isync 235a47a12beSStefan Roese mflr r0 236a47a12beSStefan Roese stwu r0, -4(r1) 237a47a12beSStefan Roese stwu r4, -4(r1) 238a47a12beSStefan Roese stwu r5, -4(r1) 239a47a12beSStefan Roese 240a47a12beSStefan Roese mtlr r3 241a47a12beSStefan Roese lwz r3, 0(r4) 242a47a12beSStefan Roese blrl 243a47a12beSStefan Roese 244a47a12beSStefan Roese lwz r5, 4(r1) 245a47a12beSStefan Roese stw r3, 0(r5) 246a47a12beSStefan Roese lwz r5, 0(r1) 247a47a12beSStefan Roese stw r4, 0(r5) 248a47a12beSStefan Roese 249a47a12beSStefan Roese lwz r0, 8(r1) 250a47a12beSStefan Roese addi r1, r1, 12 251a47a12beSStefan Roese mtlr r0 252a47a12beSStefan Roese blr 253a47a12beSStefan Roese 254a47a12beSStefan Roese/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ 255a47a12beSStefan Roese .global cpu_post_exec_21x 256a47a12beSStefan Roesecpu_post_exec_21x: 257a47a12beSStefan Roese isync 258a47a12beSStefan Roese mflr r0 259a47a12beSStefan Roese stwu r0, -4(r1) 260a47a12beSStefan Roese stwu r4, -4(r1) 261a47a12beSStefan Roese stwu r5, -4(r1) 262a47a12beSStefan Roese 263a47a12beSStefan Roese mtlr r3 264a47a12beSStefan Roese mr r3, r6 265a47a12beSStefan Roese blrl 266a47a12beSStefan Roese 267a47a12beSStefan Roese lwz r5, 4(r1) 268a47a12beSStefan Roese stw r3, 0(r5) 269a47a12beSStefan Roese lwz r5, 0(r1) 270a47a12beSStefan Roese stw r4, 0(r5) 271a47a12beSStefan Roese 272a47a12beSStefan Roese lwz r0, 8(r1) 273a47a12beSStefan Roese addi r1, r1, 12 274a47a12beSStefan Roese mtlr r0 275a47a12beSStefan Roese blr 276a47a12beSStefan Roese 277a47a12beSStefan Roese/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, 278a47a12beSStefan Roese ulong cr); */ 279a47a12beSStefan Roese .global cpu_post_exec_31 280a47a12beSStefan Roesecpu_post_exec_31: 281a47a12beSStefan Roese isync 282a47a12beSStefan Roese mflr r0 283a47a12beSStefan Roese stwu r0, -4(r1) 284a47a12beSStefan Roese stwu r4, -4(r1) 285a47a12beSStefan Roese stwu r5, -4(r1) 286a47a12beSStefan Roese stwu r6, -4(r1) 287a47a12beSStefan Roese 288a47a12beSStefan Roese mtlr r3 289a47a12beSStefan Roese lwz r3, 0(r4) 290a47a12beSStefan Roese lwz r4, 0(r5) 291a47a12beSStefan Roese mr r6, r7 292a47a12beSStefan Roese 293a47a12beSStefan Roese mfcr r7 294a47a12beSStefan Roese blrl 295a47a12beSStefan Roese mtcr r7 296a47a12beSStefan Roese 297a47a12beSStefan Roese lwz r7, 8(r1) 298a47a12beSStefan Roese stw r3, 0(r7) 299a47a12beSStefan Roese lwz r7, 4(r1) 300a47a12beSStefan Roese stw r4, 0(r7) 301a47a12beSStefan Roese lwz r7, 0(r1) 302a47a12beSStefan Roese stw r5, 0(r7) 303a47a12beSStefan Roese 304a47a12beSStefan Roese lwz r0, 12(r1) 305a47a12beSStefan Roese addi r1, r1, 16 306a47a12beSStefan Roese mtlr r0 307a47a12beSStefan Roese blr 308a47a12beSStefan Roese 309a47a12beSStefan Roese/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ 310a47a12beSStefan Roese .global cpu_post_complex_1_asm 311a47a12beSStefan Roesecpu_post_complex_1_asm: 312a47a12beSStefan Roese li r9,0 313a47a12beSStefan Roese cmpw r9,r7 314a47a12beSStefan Roese bge cpu_post_complex_1_done 315a47a12beSStefan Roese mtctr r7 316a47a12beSStefan Roesecpu_post_complex_1_loop: 317a47a12beSStefan Roese mullw r0,r3,r4 318a47a12beSStefan Roese subf r0,r5,r0 319a47a12beSStefan Roese divw r0,r0,r6 320a47a12beSStefan Roese add r9,r9,r0 321a47a12beSStefan Roese bdnz cpu_post_complex_1_loop 322a47a12beSStefan Roesecpu_post_complex_1_done: 323a47a12beSStefan Roese mr r3,r9 324a47a12beSStefan Roese blr 325a47a12beSStefan Roese 326a47a12beSStefan Roese/* int cpu_post_complex_2_asm (int x, int n); */ 327a47a12beSStefan Roese .global cpu_post_complex_2_asm 328a47a12beSStefan Roesecpu_post_complex_2_asm: 329a47a12beSStefan Roese mr. r0,r4 330a47a12beSStefan Roese mtctr r0 331a47a12beSStefan Roese mr r0,r3 332a47a12beSStefan Roese li r3,1 333a47a12beSStefan Roese li r4,1 334a47a12beSStefan Roese blelr 335a47a12beSStefan Roesecpu_post_complex_2_loop: 336a47a12beSStefan Roese mullw r3,r3,r0 337a47a12beSStefan Roese add r3,r3,r4 338a47a12beSStefan Roese bdnz cpu_post_complex_2_loop 339a47a12beSStefan Roeseblr 340a47a12beSStefan Roese 341a47a12beSStefan Roese#endif 342