xref: /openbmc/u-boot/include/zynqmp_tap_delay.h (revision 3b52847a451a81001b578353e793d7d9739b69d6) 
1*d1f4e39dSSiva Durga Prasad Paladugu /* SPDX-License-Identifier: GPL-2.0 */
2*d1f4e39dSSiva Durga Prasad Paladugu /*
3*d1f4e39dSSiva Durga Prasad Paladugu  * Xilinx ZynqMP SoC Tap Delay Programming
4*d1f4e39dSSiva Durga Prasad Paladugu  *
5*d1f4e39dSSiva Durga Prasad Paladugu  * Copyright (C) 2018 Xilinx, Inc.
6*d1f4e39dSSiva Durga Prasad Paladugu  */
7*d1f4e39dSSiva Durga Prasad Paladugu 
8*d1f4e39dSSiva Durga Prasad Paladugu #ifndef __ZYNQMP_TAP_DELAY_H__
9*d1f4e39dSSiva Durga Prasad Paladugu #define __ZYNQMP_TAP_DELAY_H__
10*d1f4e39dSSiva Durga Prasad Paladugu 
11*d1f4e39dSSiva Durga Prasad Paladugu #ifdef CONFIG_ARCH_ZYNQMP
12*d1f4e39dSSiva Durga Prasad Paladugu void zynqmp_dll_reset(u8 deviceid);
13*d1f4e39dSSiva Durga Prasad Paladugu void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
14*d1f4e39dSSiva Durga Prasad Paladugu #else
zynqmp_dll_reset(u8 deviceid)15*d1f4e39dSSiva Durga Prasad Paladugu inline void zynqmp_dll_reset(u8 deviceid) {}
arasan_zynqmp_set_tapdelay(u8 device_id,u8 uhsmode,u8 bank)16*d1f4e39dSSiva Durga Prasad Paladugu inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
17*d1f4e39dSSiva Durga Prasad Paladugu #endif
18*d1f4e39dSSiva Durga Prasad Paladugu 
19*d1f4e39dSSiva Durga Prasad Paladugu #endif
20