xref: /openbmc/u-boot/include/virtex2.h (revision d9071ce0a8cd684589c9c35e4d7c604a9cbd7d62)
1c609719bSwdenk /*
2c609719bSwdenk  * (C) Copyright 2002
3c609719bSwdenk  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4c609719bSwdenk  * Keith Outwater, keith_outwater@mvis.com
5c609719bSwdenk  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
7c609719bSwdenk  */
8c609719bSwdenk 
9c609719bSwdenk #ifndef _VIRTEX2_H_
10c609719bSwdenk #define _VIRTEX2_H_
11c609719bSwdenk 
12c609719bSwdenk #include <xilinx.h>
13c609719bSwdenk 
14*d9071ce0SMichal Simek int virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
15*d9071ce0SMichal Simek int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
16*d9071ce0SMichal Simek int virtex2_info(Xilinx_desc *desc);
17c609719bSwdenk 
18c609719bSwdenk /*
19c609719bSwdenk  * Slave SelectMap Implementation function table.
20c609719bSwdenk  */
21c609719bSwdenk typedef struct {
22c609719bSwdenk 	Xilinx_pre_fn	pre;
23c609719bSwdenk 	Xilinx_pgm_fn	pgm;
24c609719bSwdenk 	Xilinx_init_fn	init;
25c609719bSwdenk 	Xilinx_err_fn	err;
26c609719bSwdenk 	Xilinx_done_fn	done;
27c609719bSwdenk 	Xilinx_clk_fn	clk;
28c609719bSwdenk 	Xilinx_cs_fn	cs;
29c609719bSwdenk 	Xilinx_wr_fn	wr;
30c609719bSwdenk 	Xilinx_rdata_fn	rdata;
31c609719bSwdenk 	Xilinx_wdata_fn	wdata;
32c609719bSwdenk 	Xilinx_busy_fn	busy;
33c609719bSwdenk 	Xilinx_abort_fn	abort;
34c609719bSwdenk 	Xilinx_post_fn	post;
35*d9071ce0SMichal Simek } xilinx_virtex2_slave_selectmap_fns;
36c609719bSwdenk 
37c609719bSwdenk /* Slave Serial Implementation function table */
38c609719bSwdenk typedef struct {
39c609719bSwdenk 	Xilinx_pgm_fn	pgm;
40c609719bSwdenk 	Xilinx_clk_fn	clk;
41c609719bSwdenk 	Xilinx_rdata_fn	rdata;
42c609719bSwdenk 	Xilinx_wdata_fn	wdata;
43*d9071ce0SMichal Simek } xilinx_virtex2_slave_serial_fns;
44c609719bSwdenk 
45c609719bSwdenk /* Device Image Sizes (in bytes)
46c609719bSwdenk  *********************************************************************/
47c609719bSwdenk #define XILINX_XC2V40_SIZE		(338208 / 8)
48c609719bSwdenk #define XILINX_XC2V80_SIZE		(597408 / 8)
49c609719bSwdenk #define XILINX_XC2V250_SIZE		(1591584 / 8)
50c609719bSwdenk #define XILINX_XC2V500_SIZE		(2557857 / 8)
51c609719bSwdenk #define XILINX_XC2V1000_SIZE	(3749408 / 8)
52c609719bSwdenk #define XILINX_XC2V1500_SIZE	(5166240 / 8)
53c609719bSwdenk #define XILINX_XC2V2000_SIZE	(6808352 / 8)
54c609719bSwdenk #define XILINX_XC2V3000_SIZE	(9589408 / 8)
55c609719bSwdenk #define XILINX_XC2V4000_SIZE	(14220192 / 8)
56c609719bSwdenk #define XILINX_XC2V6000_SIZE	(19752096 / 8)
57c609719bSwdenk #define XILINX_XC2V8000_SIZE	(26185120 / 8)
58c609719bSwdenk #define XILINX_XC2V10000_SIZE	(33519264 / 8)
59c609719bSwdenk 
60c609719bSwdenk /* Descriptor Macros
61c609719bSwdenk  *********************************************************************/
62c609719bSwdenk #define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
63*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
64c609719bSwdenk 
65c609719bSwdenk #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
66*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
67c609719bSwdenk 
68c609719bSwdenk #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
69*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
70c609719bSwdenk 
71c609719bSwdenk #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
72*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
73c609719bSwdenk 
74c609719bSwdenk #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
75*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
76c609719bSwdenk 
77c609719bSwdenk #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
78*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
79c609719bSwdenk 
80c609719bSwdenk #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
81*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
82c609719bSwdenk 
83c609719bSwdenk #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
84*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
85c609719bSwdenk 
86c609719bSwdenk #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
87*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
88c609719bSwdenk 
89c609719bSwdenk #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
90*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
91c609719bSwdenk 
92c609719bSwdenk #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
93*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
94c609719bSwdenk 
95c609719bSwdenk #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
96*d9071ce0SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
97c609719bSwdenk 
98c609719bSwdenk #endif /* _VIRTEX2_H_ */
99