1*c609719bSwdenk /* 2*c609719bSwdenk * (C) Copyright 2002 3*c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*c609719bSwdenk * Keith Outwater, keith_outwater@mvis.com 5*c609719bSwdenk * 6*c609719bSwdenk * See file CREDITS for list of people who contributed to this 7*c609719bSwdenk * project. 8*c609719bSwdenk * 9*c609719bSwdenk * This program is free software; you can redistribute it and/or 10*c609719bSwdenk * modify it under the terms of the GNU General Public License as 11*c609719bSwdenk * published by the Free Software Foundation; either version 2 of 12*c609719bSwdenk * the License, or (at your option) any later version. 13*c609719bSwdenk * 14*c609719bSwdenk * This program is distributed in the hope that it will be useful, 15*c609719bSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*c609719bSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*c609719bSwdenk * GNU General Public License for more details. 18*c609719bSwdenk * 19*c609719bSwdenk * You should have received a copy of the GNU General Public License 20*c609719bSwdenk * along with this program; if not, write to the Free Software 21*c609719bSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*c609719bSwdenk * MA 02111-1307 USA 23*c609719bSwdenk * 24*c609719bSwdenk */ 25*c609719bSwdenk 26*c609719bSwdenk #ifndef _VIRTEX2_H_ 27*c609719bSwdenk #define _VIRTEX2_H_ 28*c609719bSwdenk 29*c609719bSwdenk #include <xilinx.h> 30*c609719bSwdenk 31*c609719bSwdenk extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); 32*c609719bSwdenk extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); 33*c609719bSwdenk extern int Virtex2_info( Xilinx_desc *desc ); 34*c609719bSwdenk extern int Virtex2_reloc( Xilinx_desc *desc, ulong reloc_off ); 35*c609719bSwdenk 36*c609719bSwdenk /* 37*c609719bSwdenk * Slave SelectMap Implementation function table. 38*c609719bSwdenk */ 39*c609719bSwdenk typedef struct { 40*c609719bSwdenk Xilinx_pre_fn pre; 41*c609719bSwdenk Xilinx_pgm_fn pgm; 42*c609719bSwdenk Xilinx_init_fn init; 43*c609719bSwdenk Xilinx_err_fn err; 44*c609719bSwdenk Xilinx_done_fn done; 45*c609719bSwdenk Xilinx_clk_fn clk; 46*c609719bSwdenk Xilinx_cs_fn cs; 47*c609719bSwdenk Xilinx_wr_fn wr; 48*c609719bSwdenk Xilinx_rdata_fn rdata; 49*c609719bSwdenk Xilinx_wdata_fn wdata; 50*c609719bSwdenk Xilinx_busy_fn busy; 51*c609719bSwdenk Xilinx_abort_fn abort; 52*c609719bSwdenk Xilinx_post_fn post; 53*c609719bSwdenk int relocated; 54*c609719bSwdenk } Xilinx_Virtex2_Slave_SelectMap_fns; 55*c609719bSwdenk 56*c609719bSwdenk /* Slave Serial Implementation function table */ 57*c609719bSwdenk typedef struct { 58*c609719bSwdenk Xilinx_pgm_fn pgm; 59*c609719bSwdenk Xilinx_clk_fn clk; 60*c609719bSwdenk Xilinx_rdata_fn rdata; 61*c609719bSwdenk Xilinx_wdata_fn wdata; 62*c609719bSwdenk int relocated; 63*c609719bSwdenk } Xilinx_Virtex2_Slave_Serial_fns; 64*c609719bSwdenk 65*c609719bSwdenk /* Device Image Sizes (in bytes) 66*c609719bSwdenk *********************************************************************/ 67*c609719bSwdenk #define XILINX_XC2V40_SIZE (338208 / 8) 68*c609719bSwdenk #define XILINX_XC2V80_SIZE (597408 / 8) 69*c609719bSwdenk #define XILINX_XC2V250_SIZE (1591584 / 8) 70*c609719bSwdenk #define XILINX_XC2V500_SIZE (2557857 / 8) 71*c609719bSwdenk #define XILINX_XC2V1000_SIZE (3749408 / 8) 72*c609719bSwdenk #define XILINX_XC2V1500_SIZE (5166240 / 8) 73*c609719bSwdenk #define XILINX_XC2V2000_SIZE (6808352 / 8) 74*c609719bSwdenk #define XILINX_XC2V3000_SIZE (9589408 / 8) 75*c609719bSwdenk #define XILINX_XC2V4000_SIZE (14220192 / 8) 76*c609719bSwdenk #define XILINX_XC2V6000_SIZE (19752096 / 8) 77*c609719bSwdenk #define XILINX_XC2V8000_SIZE (26185120 / 8) 78*c609719bSwdenk #define XILINX_XC2V10000_SIZE (33519264 / 8) 79*c609719bSwdenk 80*c609719bSwdenk /* Descriptor Macros 81*c609719bSwdenk *********************************************************************/ 82*c609719bSwdenk #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ 83*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } 84*c609719bSwdenk 85*c609719bSwdenk #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ 86*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } 87*c609719bSwdenk 88*c609719bSwdenk #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ 89*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } 90*c609719bSwdenk 91*c609719bSwdenk #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ 92*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } 93*c609719bSwdenk 94*c609719bSwdenk #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ 95*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } 96*c609719bSwdenk 97*c609719bSwdenk #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ 98*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } 99*c609719bSwdenk 100*c609719bSwdenk #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ 101*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } 102*c609719bSwdenk 103*c609719bSwdenk #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ 104*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } 105*c609719bSwdenk 106*c609719bSwdenk #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ 107*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } 108*c609719bSwdenk 109*c609719bSwdenk #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ 110*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } 111*c609719bSwdenk 112*c609719bSwdenk #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ 113*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } 114*c609719bSwdenk 115*c609719bSwdenk #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ 116*c609719bSwdenk { Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } 117*c609719bSwdenk 118*c609719bSwdenk #endif /* _VIRTEX2_H_ */ 119*c609719bSwdenk 120*c609719bSwdenk /* vim: set ts=4 tw=78: */ 121