1c609719bSwdenk /* 2c609719bSwdenk * (C) Copyright 2002 3c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4c609719bSwdenk * Keith Outwater, keith_outwater@mvis.com 5c609719bSwdenk * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7c609719bSwdenk */ 8c609719bSwdenk 9c609719bSwdenk #ifndef _VIRTEX2_H_ 10c609719bSwdenk #define _VIRTEX2_H_ 11c609719bSwdenk 12c609719bSwdenk #include <xilinx.h> 13c609719bSwdenk 14c609719bSwdenk /* 15c609719bSwdenk * Slave SelectMap Implementation function table. 16c609719bSwdenk */ 17c609719bSwdenk typedef struct { 182df9d5c4SMichal Simek xilinx_pre_fn pre; 192df9d5c4SMichal Simek xilinx_pgm_fn pgm; 202df9d5c4SMichal Simek xilinx_init_fn init; 212df9d5c4SMichal Simek xilinx_err_fn err; 222df9d5c4SMichal Simek xilinx_done_fn done; 232df9d5c4SMichal Simek xilinx_clk_fn clk; 242df9d5c4SMichal Simek xilinx_cs_fn cs; 252df9d5c4SMichal Simek xilinx_wr_fn wr; 262df9d5c4SMichal Simek xilinx_rdata_fn rdata; 272df9d5c4SMichal Simek xilinx_wdata_fn wdata; 282df9d5c4SMichal Simek xilinx_busy_fn busy; 292df9d5c4SMichal Simek xilinx_abort_fn abort; 302df9d5c4SMichal Simek xilinx_post_fn post; 31d9071ce0SMichal Simek } xilinx_virtex2_slave_selectmap_fns; 32c609719bSwdenk 33c609719bSwdenk /* Slave Serial Implementation function table */ 34c609719bSwdenk typedef struct { 352df9d5c4SMichal Simek xilinx_pgm_fn pgm; 362df9d5c4SMichal Simek xilinx_clk_fn clk; 372df9d5c4SMichal Simek xilinx_rdata_fn rdata; 382df9d5c4SMichal Simek xilinx_wdata_fn wdata; 39d9071ce0SMichal Simek } xilinx_virtex2_slave_serial_fns; 40c609719bSwdenk 41*6a6acd12SMichal Simek #if defined(CONFIG_FPGA_VIRTEX2) 42*6a6acd12SMichal Simek extern struct xilinx_fpga_op virtex2_op; 43*6a6acd12SMichal Simek # define FPGA_VIRTEX2_OPS &virtex2_op 44*6a6acd12SMichal Simek #else 45*6a6acd12SMichal Simek # define FPGA_VIRTEX2_OPS NULL 46*6a6acd12SMichal Simek #endif 47*6a6acd12SMichal Simek 48c609719bSwdenk /* Device Image Sizes (in bytes) 49c609719bSwdenk *********************************************************************/ 50c609719bSwdenk #define XILINX_XC2V40_SIZE (338208 / 8) 51c609719bSwdenk #define XILINX_XC2V80_SIZE (597408 / 8) 52c609719bSwdenk #define XILINX_XC2V250_SIZE (1591584 / 8) 53c609719bSwdenk #define XILINX_XC2V500_SIZE (2557857 / 8) 54c609719bSwdenk #define XILINX_XC2V1000_SIZE (3749408 / 8) 55c609719bSwdenk #define XILINX_XC2V1500_SIZE (5166240 / 8) 56c609719bSwdenk #define XILINX_XC2V2000_SIZE (6808352 / 8) 57c609719bSwdenk #define XILINX_XC2V3000_SIZE (9589408 / 8) 58c609719bSwdenk #define XILINX_XC2V4000_SIZE (14220192 / 8) 59c609719bSwdenk #define XILINX_XC2V6000_SIZE (19752096 / 8) 60c609719bSwdenk #define XILINX_XC2V8000_SIZE (26185120 / 8) 61c609719bSwdenk #define XILINX_XC2V10000_SIZE (33519264 / 8) 62c609719bSwdenk 63c609719bSwdenk /* Descriptor Macros 64c609719bSwdenk *********************************************************************/ 65c609719bSwdenk #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ 66*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ 67*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 68c609719bSwdenk 69c609719bSwdenk #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ 70*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ 71*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 72c609719bSwdenk 73c609719bSwdenk #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ 74*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ 75*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 76c609719bSwdenk 77c609719bSwdenk #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ 78*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ 79*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 80c609719bSwdenk 81c609719bSwdenk #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ 82*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ 83*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 84c609719bSwdenk 85c609719bSwdenk #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ 86*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ 87*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 88c609719bSwdenk 89c609719bSwdenk #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ 90*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ 91*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 92c609719bSwdenk 93c609719bSwdenk #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ 94*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ 95*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 96c609719bSwdenk 97c609719bSwdenk #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ 98*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ 99*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 100c609719bSwdenk 101c609719bSwdenk #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ 102*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ 103*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 104c609719bSwdenk 105c609719bSwdenk #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ 106*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ 107*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 108c609719bSwdenk 109c609719bSwdenk #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ 110*6a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ 111*6a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 112c609719bSwdenk 113c609719bSwdenk #endif /* _VIRTEX2_H_ */ 114