1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c609719bSwdenk /* 3c609719bSwdenk * (C) Copyright 2002 4c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5c609719bSwdenk * Keith Outwater, keith_outwater@mvis.com 6c609719bSwdenk */ 7c609719bSwdenk 8c609719bSwdenk #ifndef _VIRTEX2_H_ 9c609719bSwdenk #define _VIRTEX2_H_ 10c609719bSwdenk 11c609719bSwdenk #include <xilinx.h> 12c609719bSwdenk 13c609719bSwdenk /* 14c609719bSwdenk * Slave SelectMap Implementation function table. 15c609719bSwdenk */ 16c609719bSwdenk typedef struct { 172df9d5c4SMichal Simek xilinx_pre_fn pre; 182df9d5c4SMichal Simek xilinx_pgm_fn pgm; 192df9d5c4SMichal Simek xilinx_init_fn init; 202df9d5c4SMichal Simek xilinx_err_fn err; 212df9d5c4SMichal Simek xilinx_done_fn done; 222df9d5c4SMichal Simek xilinx_clk_fn clk; 232df9d5c4SMichal Simek xilinx_cs_fn cs; 242df9d5c4SMichal Simek xilinx_wr_fn wr; 252df9d5c4SMichal Simek xilinx_rdata_fn rdata; 262df9d5c4SMichal Simek xilinx_wdata_fn wdata; 272df9d5c4SMichal Simek xilinx_busy_fn busy; 282df9d5c4SMichal Simek xilinx_abort_fn abort; 292df9d5c4SMichal Simek xilinx_post_fn post; 30d9071ce0SMichal Simek } xilinx_virtex2_slave_selectmap_fns; 31c609719bSwdenk 32c609719bSwdenk /* Slave Serial Implementation function table */ 33c609719bSwdenk typedef struct { 342df9d5c4SMichal Simek xilinx_pgm_fn pgm; 352df9d5c4SMichal Simek xilinx_clk_fn clk; 362df9d5c4SMichal Simek xilinx_rdata_fn rdata; 372df9d5c4SMichal Simek xilinx_wdata_fn wdata; 38d9071ce0SMichal Simek } xilinx_virtex2_slave_serial_fns; 39c609719bSwdenk 406a6acd12SMichal Simek #if defined(CONFIG_FPGA_VIRTEX2) 416a6acd12SMichal Simek extern struct xilinx_fpga_op virtex2_op; 426a6acd12SMichal Simek # define FPGA_VIRTEX2_OPS &virtex2_op 436a6acd12SMichal Simek #else 446a6acd12SMichal Simek # define FPGA_VIRTEX2_OPS NULL 456a6acd12SMichal Simek #endif 466a6acd12SMichal Simek 47c609719bSwdenk /* Device Image Sizes (in bytes) 48c609719bSwdenk *********************************************************************/ 49c609719bSwdenk #define XILINX_XC2V40_SIZE (338208 / 8) 50c609719bSwdenk #define XILINX_XC2V80_SIZE (597408 / 8) 51c609719bSwdenk #define XILINX_XC2V250_SIZE (1591584 / 8) 52c609719bSwdenk #define XILINX_XC2V500_SIZE (2557857 / 8) 53c609719bSwdenk #define XILINX_XC2V1000_SIZE (3749408 / 8) 54c609719bSwdenk #define XILINX_XC2V1500_SIZE (5166240 / 8) 55c609719bSwdenk #define XILINX_XC2V2000_SIZE (6808352 / 8) 56c609719bSwdenk #define XILINX_XC2V3000_SIZE (9589408 / 8) 57c609719bSwdenk #define XILINX_XC2V4000_SIZE (14220192 / 8) 58c609719bSwdenk #define XILINX_XC2V6000_SIZE (19752096 / 8) 59c609719bSwdenk #define XILINX_XC2V8000_SIZE (26185120 / 8) 60c609719bSwdenk #define XILINX_XC2V10000_SIZE (33519264 / 8) 61c609719bSwdenk 62c609719bSwdenk /* Descriptor Macros 63c609719bSwdenk *********************************************************************/ 64c609719bSwdenk #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ 656a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ 666a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 67c609719bSwdenk 68c609719bSwdenk #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ 696a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ 706a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 71c609719bSwdenk 72c609719bSwdenk #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ 736a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ 746a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 75c609719bSwdenk 76c609719bSwdenk #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ 776a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ 786a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 79c609719bSwdenk 80c609719bSwdenk #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ 816a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ 826a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 83c609719bSwdenk 84c609719bSwdenk #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ 856a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ 866a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 87c609719bSwdenk 88c609719bSwdenk #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ 896a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ 906a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 91c609719bSwdenk 92c609719bSwdenk #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ 936a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ 946a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 95c609719bSwdenk 96c609719bSwdenk #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ 976a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ 986a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 99c609719bSwdenk 100c609719bSwdenk #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ 1016a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ 1026a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 103c609719bSwdenk 104c609719bSwdenk #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ 1056a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ 1066a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 107c609719bSwdenk 108c609719bSwdenk #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ 1096a6acd12SMichal Simek { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ 1106a6acd12SMichal Simek FPGA_VIRTEX2_OPS } 111c609719bSwdenk 112c609719bSwdenk #endif /* _VIRTEX2_H_ */ 113