1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2256e4be8Sstroese /* 3256e4be8Sstroese * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com 4256e4be8Sstroese */ 5256e4be8Sstroese 6256e4be8Sstroese #ifndef _universe_h 7256e4be8Sstroese #define _universe_h 8256e4be8Sstroese 9256e4be8Sstroese typedef struct _UNIVERSE UNIVERSE; 10256e4be8Sstroese typedef struct _SLAVE_IMAGE SLAVE_IMAGE; 11256e4be8Sstroese typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; 12256e4be8Sstroese 13256e4be8Sstroese struct _SLAVE_IMAGE { 14256e4be8Sstroese unsigned int ctl; /* Control */ 15256e4be8Sstroese unsigned int bs; /* Base */ 16256e4be8Sstroese unsigned int bd; /* Bound */ 17256e4be8Sstroese unsigned int to; /* Translation */ 18256e4be8Sstroese unsigned int reserved; 19256e4be8Sstroese }; 20256e4be8Sstroese 21256e4be8Sstroese struct _UNIVERSE { 22256e4be8Sstroese unsigned int pci_id; 23256e4be8Sstroese unsigned int pci_csr; 24256e4be8Sstroese unsigned int pci_class; 25256e4be8Sstroese unsigned int pci_misc0; 26256e4be8Sstroese unsigned int pci_bs; 27256e4be8Sstroese unsigned int spare0[10]; 28256e4be8Sstroese unsigned int pci_misc1; 29256e4be8Sstroese unsigned int spare1[48]; 30256e4be8Sstroese SLAVE_IMAGE lsi[4]; 31256e4be8Sstroese unsigned int spare2[8]; 32256e4be8Sstroese unsigned int scyc_ctl; 33256e4be8Sstroese unsigned int scyc_addr; 34256e4be8Sstroese unsigned int scyc_en; 35256e4be8Sstroese unsigned int scyc_cmp; 36256e4be8Sstroese unsigned int scyc_swp; 37256e4be8Sstroese unsigned int lmisc; 38256e4be8Sstroese unsigned int slsi; 39256e4be8Sstroese unsigned int l_cmderr; 40256e4be8Sstroese unsigned int laerr; 41256e4be8Sstroese unsigned int spare3[27]; 42256e4be8Sstroese unsigned int dctl; 43256e4be8Sstroese unsigned int dtbc; 44256e4be8Sstroese unsigned int dla; 45256e4be8Sstroese unsigned int spare4[1]; 46256e4be8Sstroese unsigned int dva; 47256e4be8Sstroese unsigned int spare5[1]; 48256e4be8Sstroese unsigned int dcpp; 49256e4be8Sstroese unsigned int spare6[1]; 50256e4be8Sstroese unsigned int dgcs; 51256e4be8Sstroese unsigned int d_llue; 52256e4be8Sstroese unsigned int spare7[54]; 53256e4be8Sstroese unsigned int lint_en; 54256e4be8Sstroese unsigned int lint_stat; 55256e4be8Sstroese unsigned int lint_map0; 56256e4be8Sstroese unsigned int lint_map1; 57256e4be8Sstroese unsigned int vint_en; 58256e4be8Sstroese unsigned int vint_stat; 59256e4be8Sstroese unsigned int vint_map0; 60256e4be8Sstroese unsigned int vint_map1; 61256e4be8Sstroese unsigned int statid; 62256e4be8Sstroese unsigned int vx_statid[7]; 63256e4be8Sstroese unsigned int spare8[48]; 64256e4be8Sstroese unsigned int mast_ctl; 65256e4be8Sstroese unsigned int misc_ctl; 66256e4be8Sstroese unsigned int misc_stat; 67256e4be8Sstroese unsigned int user_am; 68256e4be8Sstroese unsigned int spare9[700]; 69256e4be8Sstroese SLAVE_IMAGE vsi[4]; 70256e4be8Sstroese unsigned int spare10[8]; 71256e4be8Sstroese unsigned int vrai_ctl; 72256e4be8Sstroese unsigned int vrai_bs; 73256e4be8Sstroese unsigned int spare11[2]; 74256e4be8Sstroese unsigned int vcsr_ctl; 75256e4be8Sstroese unsigned int vcsr_to; 76256e4be8Sstroese unsigned int v_amerr; 77256e4be8Sstroese unsigned int vaerr; 78256e4be8Sstroese unsigned int spare12[25]; 79256e4be8Sstroese unsigned int vcsr_clr; 80256e4be8Sstroese unsigned int vcsr_set; 81256e4be8Sstroese unsigned int vcsr_bs; 82256e4be8Sstroese }; 83256e4be8Sstroese 84256e4be8Sstroese #define IRQ_VOWN 0x0001 85256e4be8Sstroese #define IRQ_VIRQ1 0x0002 86256e4be8Sstroese #define IRQ_VIRQ2 0x0004 87256e4be8Sstroese #define IRQ_VIRQ3 0x0008 88256e4be8Sstroese #define IRQ_VIRQ4 0x0010 89256e4be8Sstroese #define IRQ_VIRQ5 0x0020 90256e4be8Sstroese #define IRQ_VIRQ6 0x0040 91256e4be8Sstroese #define IRQ_VIRQ7 0x0080 92256e4be8Sstroese #define IRQ_DMA 0x0100 93256e4be8Sstroese #define IRQ_LERR 0x0200 94256e4be8Sstroese #define IRQ_VERR 0x0400 95256e4be8Sstroese #define IRQ_res 0x0800 96256e4be8Sstroese #define IRQ_IACK 0x1000 97256e4be8Sstroese #define IRQ_SWINT 0x2000 98256e4be8Sstroese #define IRQ_SYSFAIL 0x4000 99256e4be8Sstroese #define IRQ_ACFAIL 0x8000 100256e4be8Sstroese 101256e4be8Sstroese struct _TDMA_CMD_PACKET { 102256e4be8Sstroese unsigned int dctl; /* DMA Control */ 103256e4be8Sstroese unsigned int dtbc; /* Transfer Byte Count */ 104256e4be8Sstroese unsigned int dlv; /* PCI Address */ 105256e4be8Sstroese unsigned int res1; /* Reserved */ 106256e4be8Sstroese unsigned int dva; /* Vme Address */ 107256e4be8Sstroese unsigned int res2; /* Reserved */ 108256e4be8Sstroese unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 109256e4be8Sstroese unsigned int res3; /* Reserved */ 110256e4be8Sstroese }; 111256e4be8Sstroese 112256e4be8Sstroese #define VME_AM_A16 0x01 113256e4be8Sstroese #define VME_AM_A24 0x02 114256e4be8Sstroese #define VME_AM_A32 0x03 115256e4be8Sstroese #define VME_AM_Axx 0x03 116256e4be8Sstroese #define VME_AM_SUP 0x04 117256e4be8Sstroese #define VME_AM_DATA 0x10 118256e4be8Sstroese #define VME_AM_PROG 0x20 119256e4be8Sstroese #define VME_AM_Mxx 0x30 120256e4be8Sstroese 121256e4be8Sstroese #define VME_FLAG_D8 0x01 122256e4be8Sstroese #define VME_FLAG_D16 0x02 123256e4be8Sstroese #define VME_FLAG_D32 0x03 124256e4be8Sstroese #define VME_FLAG_Dxx 0x03 125256e4be8Sstroese 126256e4be8Sstroese #define PCI_MS_MEM 0x01 127256e4be8Sstroese #define PCI_MS_IO 0x02 128256e4be8Sstroese #define PCI_MS_CONFIG 0x03 129256e4be8Sstroese #define PCI_MS_Mxx 0x03 130256e4be8Sstroese 131256e4be8Sstroese #endif 132