xref: /openbmc/u-boot/include/stm32_rcc.h (revision 4e97e25723530cc8bf57ca1d0ae17d86895e04c5)
1 /*
2  * Copyright (C) STMicroelectronics SA 2017
3  * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __STM32_RCC_H_
9 #define __STM32_RCC_H_
10 
11 #define AHB_PSC_1			0
12 #define AHB_PSC_2			0x8
13 #define AHB_PSC_4			0x9
14 #define AHB_PSC_8			0xA
15 #define AHB_PSC_16			0xB
16 #define AHB_PSC_64			0xC
17 #define AHB_PSC_128			0xD
18 #define AHB_PSC_256			0xE
19 #define AHB_PSC_512			0xF
20 
21 #define APB_PSC_1			0
22 #define APB_PSC_2			0x4
23 #define APB_PSC_4			0x5
24 #define APB_PSC_8			0x6
25 #define APB_PSC_16			0x7
26 
27 struct pll_psc {
28 	u8	pll_m;
29 	u16	pll_n;
30 	u8	pll_p;
31 	u8	pll_q;
32 	u8	ahb_psc;
33 	u8	apb1_psc;
34 	u8	apb2_psc;
35 };
36 
37 struct stm32_clk_info {
38 	struct pll_psc sys_pll_psc;
39 	bool has_overdrive;
40 	bool v2;
41 };
42 
43 enum soc_family {
44 	STM32F4,
45 	STM32F7,
46 };
47 
48 struct stm32_rcc_clk {
49 	char *drv_name;
50 	enum soc_family soc;
51 };
52 
53 #endif /* __STM32_RCC_H_ */
54