xref: /openbmc/u-boot/include/smsc_sio1007.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
298af34f8SBin Meng /*
398af34f8SBin Meng  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
498af34f8SBin Meng  */
598af34f8SBin Meng 
698af34f8SBin Meng #ifndef _SMSC_SIO1007_H_
798af34f8SBin Meng #define _SMSC_SIO1007_H_
898af34f8SBin Meng 
998af34f8SBin Meng /*
1098af34f8SBin Meng  * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
1198af34f8SBin Meng  * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
1298af34f8SBin Meng  * SYSOPT0 and SYSOPT1 determines one of the following addresses.
1398af34f8SBin Meng  */
1498af34f8SBin Meng #define SIO1007_IOPORT0		0x002e
1598af34f8SBin Meng #define SIO1007_IOPORT1		0x004e
1698af34f8SBin Meng #define SIO1007_IOPORT2		0x162e
1798af34f8SBin Meng #define SIO1007_IOPORT3		0x164e
1898af34f8SBin Meng 
1998af34f8SBin Meng /* SIO1007 registers */
2098af34f8SBin Meng 
2198af34f8SBin Meng #define DEV_POWER_CTRL		0x02
2298af34f8SBin Meng #define UART1_POWER_ON		(1 << 3)
2398af34f8SBin Meng #define UART2_POWER_ON		(1 << 7)
2498af34f8SBin Meng 
2598af34f8SBin Meng #define UART1_IOBASE		0x24
2698af34f8SBin Meng #define UART2_IOBASE		0x25
2798af34f8SBin Meng #define UART_IRQ		0x28
2898af34f8SBin Meng 
2998af34f8SBin Meng #define RTR_IOBASE_HIGH		0x21
3098af34f8SBin Meng #define RTR_IOBASE_LOW		0x30
3198af34f8SBin Meng 
3298af34f8SBin Meng #define GPIO0_DIR		0x31
3398af34f8SBin Meng #define GPIO1_DIR		0x35
3498af34f8SBin Meng #define GPIO_DIR_INPUT		0
3598af34f8SBin Meng #define GPIO_DIR_OUTPUT		1
3698af34f8SBin Meng 
3798af34f8SBin Meng #define GPIO0_POL		0x32
3898af34f8SBin Meng #define GPIO1_POL		0x36
3998af34f8SBin Meng #define GPIO_POL_NO_INVERT	0
4098af34f8SBin Meng #define GPIO_POL_INVERT		1
4198af34f8SBin Meng 
4298af34f8SBin Meng #define GPIO0_TYPE		0x33
4398af34f8SBin Meng #define GPIO1_TYPE		0x37
4498af34f8SBin Meng #define GPIO_TYPE_PUSH_PULL	0
4598af34f8SBin Meng #define GPIO_TYPE_OPEN_DRAIN	1
4698af34f8SBin Meng 
4798af34f8SBin Meng #define DEV_ACTIVATE		0x3a
4898af34f8SBin Meng #define RTR_EN			(1 << 1)
4998af34f8SBin Meng 
5098af34f8SBin Meng /* Runtime register offset */
5198af34f8SBin Meng 
5298af34f8SBin Meng #define GPIO0_DATA		0xc
5398af34f8SBin Meng #define GPIO1_DATA		0xe
5498af34f8SBin Meng 
5598af34f8SBin Meng /* Number of serial ports supported */
5698af34f8SBin Meng #define SIO1007_UART_NUM	2
5798af34f8SBin Meng 
5898af34f8SBin Meng /* Number of gpio pins supported */
5998af34f8SBin Meng #define GPIO_NUM_PER_GROUP	8
6098af34f8SBin Meng #define GPIO_GROUP_NUM		2
6198af34f8SBin Meng #define SIO1007_GPIO_NUM	(GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
6298af34f8SBin Meng 
6398af34f8SBin Meng /**
6498af34f8SBin Meng  * Configure the I/O port address of the specified serial device and
6598af34f8SBin Meng  * enable the serial device.
6698af34f8SBin Meng  *
6798af34f8SBin Meng  * @port:	SIO1007 I/O port address
6898af34f8SBin Meng  * @num:	serial device number (0 or 1)
6998af34f8SBin Meng  * @iobase:	processor I/O port address to assign to this serial device
7098af34f8SBin Meng  * @irq:	processor IRQ number to assign to this serial device
7198af34f8SBin Meng  */
7298af34f8SBin Meng void sio1007_enable_serial(int port, int num, int iobase, int irq);
7398af34f8SBin Meng 
7498af34f8SBin Meng /**
7598af34f8SBin Meng  * Configure the I/O port address of the runtime register block and
7698af34f8SBin Meng  * enable the address decoding.
7798af34f8SBin Meng  *
7898af34f8SBin Meng  * @port:	SIO1007 I/O port address
7998af34f8SBin Meng  * @iobase:	processor I/O port address to assign to the runtime registers
8098af34f8SBin Meng  */
8198af34f8SBin Meng void sio1007_enable_runtime(int port, int iobase);
8298af34f8SBin Meng 
8398af34f8SBin Meng /**
8498af34f8SBin Meng  * Configure the direction/polority/type of a specified GPIO pin
8598af34f8SBin Meng  *
8698af34f8SBin Meng  * @port:	SIO1007 I/O port address
8798af34f8SBin Meng  * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
8898af34f8SBin Meng  * @dir:	GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
8998af34f8SBin Meng  * @pol:	GPIO_POL_NO_INVERT or GPIO_POL_INVERT
9098af34f8SBin Meng  * @type:	GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
9198af34f8SBin Meng  */
9298af34f8SBin Meng void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
9398af34f8SBin Meng 
9498af34f8SBin Meng /**
9598af34f8SBin Meng  * Get a GPIO pin value.
9698af34f8SBin Meng  * This will work whether the GPIO is an input or an output.
9798af34f8SBin Meng  *
9898af34f8SBin Meng  * @port:	runtime register block I/O port address
9998af34f8SBin Meng  * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
10098af34f8SBin Meng  * @return:	0 if low, 1 if high, -EINVAL if gpio number is invalid
10198af34f8SBin Meng  */
10298af34f8SBin Meng int sio1007_gpio_get_value(int port, int gpio);
10398af34f8SBin Meng 
10498af34f8SBin Meng /**
10598af34f8SBin Meng  * Set a GPIO pin value.
10698af34f8SBin Meng  * This will only work when the GPIO is configured as an output.
10798af34f8SBin Meng  *
10898af34f8SBin Meng  * @port:	runtime register block I/O port address
10998af34f8SBin Meng  * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
11098af34f8SBin Meng  * @val:	0 if low, 1 if high
11198af34f8SBin Meng  */
11298af34f8SBin Meng void sio1007_gpio_set_value(int port, int gpio, int val);
11398af34f8SBin Meng 
11498af34f8SBin Meng #endif /* _SMSC_SIO1007_H_ */
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