183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26173c45bSThierry Reding /* 36173c45bSThierry Reding * Copyright (C) 2014 NVIDIA Corporation 46173c45bSThierry Reding */ 56173c45bSThierry Reding 66173c45bSThierry Reding #ifndef __POWER_AS3722_H__ 76173c45bSThierry Reding #define __POWER_AS3722_H__ 86173c45bSThierry Reding 96173c45bSThierry Reding #define AS3722_GPIO_OUTPUT_VDDH (1 << 0) 106173c45bSThierry Reding #define AS3722_GPIO_INVERT (1 << 1) 116173c45bSThierry Reding 12deea211aSSimon Glass #define AS3722_DEVICE_ID 0x0c 13deea211aSSimon Glass #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) 14deea211aSSimon Glass #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) 15deea211aSSimon Glass #define AS3722_SD_CONTROL 0x4d 164616e33bSMarcel Ziswiler #define AS3722_LDO_CONTROL0 0x4e 174616e33bSMarcel Ziswiler #define AS3722_LDO_CONTROL1 0x4f 18deea211aSSimon Glass #define AS3722_ASIC_ID1 0x90 19deea211aSSimon Glass #define AS3722_ASIC_ID2 0x91 20deea211aSSimon Glass 21c2012cb4SSimon Glass #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) 22e3f44f5cSSimon Glass #define AS3722_GPIO_SIGNAL_OUT 0x20 23c2012cb4SSimon Glass #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) 24c2012cb4SSimon Glass #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) 25c2012cb4SSimon Glass #define AS3722_GPIO_CONTROL_INVERT (1 << 7) 26c2012cb4SSimon Glass 27e3f44f5cSSimon Glass int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value); 28*de429751SMarcel Ziswiler int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value); 296173c45bSThierry Reding 306173c45bSThierry Reding #endif /* __POWER_AS3722_H__ */ 31