1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cf4c3448SCalvin Johnson /* 3cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 4cf4c3448SCalvin Johnson * Copyright 2017 NXP 5cf4c3448SCalvin Johnson */ 6cf4c3448SCalvin Johnson 7cf4c3448SCalvin Johnson #ifndef _HIF_H_ 8cf4c3448SCalvin Johnson #define _HIF_H_ 9cf4c3448SCalvin Johnson 10cf4c3448SCalvin Johnson /* 11cf4c3448SCalvin Johnson * @file hif.h. 12cf4c3448SCalvin Johnson * hif - PFE hif block control and status register. 13cf4c3448SCalvin Johnson * Mapped on CBUS and accessible from all PE's and ARM. 14cf4c3448SCalvin Johnson */ 15cf4c3448SCalvin Johnson #define HIF_VERSION (HIF_BASE_ADDR + 0x00) 16cf4c3448SCalvin Johnson #define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) 17cf4c3448SCalvin Johnson #define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) 18cf4c3448SCalvin Johnson #define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) 19cf4c3448SCalvin Johnson #define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) 20cf4c3448SCalvin Johnson #define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) 21cf4c3448SCalvin Johnson #define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) 22cf4c3448SCalvin Johnson #define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) 23cf4c3448SCalvin Johnson #define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) 24cf4c3448SCalvin Johnson #define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) 25cf4c3448SCalvin Johnson #define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) 26cf4c3448SCalvin Johnson #define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) 27cf4c3448SCalvin Johnson #define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) 28cf4c3448SCalvin Johnson #define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) 29cf4c3448SCalvin Johnson #define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) 30cf4c3448SCalvin Johnson #define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) 31cf4c3448SCalvin Johnson #define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) 32cf4c3448SCalvin Johnson #define HIF_AXI_CTRL (HIF_BASE_ADDR + 0x54) 33cf4c3448SCalvin Johnson 34cf4c3448SCalvin Johnson /* HIF_TX_CTRL bits */ 35cf4c3448SCalvin Johnson #define HIF_CTRL_DMA_EN BIT(0) 36cf4c3448SCalvin Johnson #define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1) 37cf4c3448SCalvin Johnson #define HIF_CTRL_BDP_CH_START_WSTB BIT(2) 38cf4c3448SCalvin Johnson 39cf4c3448SCalvin Johnson /* HIF_RX_STATUS bits */ 40cf4c3448SCalvin Johnson #define BDP_CSR_RX_DMA_ACTV BIT(16) 41cf4c3448SCalvin Johnson 42cf4c3448SCalvin Johnson /* HIF_INT_ENABLE bits */ 43cf4c3448SCalvin Johnson #define HIF_INT_EN BIT(0) 44cf4c3448SCalvin Johnson #define HIF_RXBD_INT_EN BIT(1) 45cf4c3448SCalvin Johnson #define HIF_RXPKT_INT_EN BIT(2) 46cf4c3448SCalvin Johnson #define HIF_TXBD_INT_EN BIT(3) 47cf4c3448SCalvin Johnson #define HIF_TXPKT_INT_EN BIT(4) 48cf4c3448SCalvin Johnson 49cf4c3448SCalvin Johnson /* HIF_POLL_CTRL bits*/ 50cf4c3448SCalvin Johnson #define HIF_RX_POLL_CTRL_CYCLE 0x0400 51cf4c3448SCalvin Johnson #define HIF_TX_POLL_CTRL_CYCLE 0x0400 52cf4c3448SCalvin Johnson 53cf4c3448SCalvin Johnson /* Buffer descriptor control bits */ 54cf4c3448SCalvin Johnson #define BD_CTRL_BUFLEN_MASK (0xffff) 55cf4c3448SCalvin Johnson #define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK) 56cf4c3448SCalvin Johnson #define BD_CTRL_CBD_INT_EN BIT(16) 57cf4c3448SCalvin Johnson #define BD_CTRL_PKT_INT_EN BIT(17) 58cf4c3448SCalvin Johnson #define BD_CTRL_LIFM BIT(18) 59cf4c3448SCalvin Johnson #define BD_CTRL_LAST_BD BIT(19) 60cf4c3448SCalvin Johnson #define BD_CTRL_DIR BIT(20) 61cf4c3448SCalvin Johnson #define BD_CTRL_PKT_XFER BIT(24) 62cf4c3448SCalvin Johnson #define BD_CTRL_DESC_EN BIT(31) 63cf4c3448SCalvin Johnson #define BD_CTRL_PARSE_DISABLE BIT(25) 64cf4c3448SCalvin Johnson #define BD_CTRL_BRFETCH_DISABLE BIT(26) 65cf4c3448SCalvin Johnson #define BD_CTRL_RTFETCH_DISABLE BIT(27) 66cf4c3448SCalvin Johnson 67cf4c3448SCalvin Johnson #endif /* _HIF_H_ */ 68