1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e5f495d1SPrafulla Wadaskar /* 3e5f495d1SPrafulla Wadaskar * (C) Copyright 2010 4e5f495d1SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 5e5f495d1SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6e5f495d1SPrafulla Wadaskar */ 7e5f495d1SPrafulla Wadaskar 8e5f495d1SPrafulla Wadaskar #ifndef __MVMFP_H 9e5f495d1SPrafulla Wadaskar #define __MVMFP_H 10e5f495d1SPrafulla Wadaskar 11e5f495d1SPrafulla Wadaskar /* 12e5f495d1SPrafulla Wadaskar * Header file for MultiFunctionPin (MFP) Configururation framework 13e5f495d1SPrafulla Wadaskar * 14e5f495d1SPrafulla Wadaskar * Processors Supported: 15e5f495d1SPrafulla Wadaskar * 1. Marvell ARMADA100 Processors 16e5f495d1SPrafulla Wadaskar * 17e5f495d1SPrafulla Wadaskar * processor to be supported should be added here 18e5f495d1SPrafulla Wadaskar */ 19e5f495d1SPrafulla Wadaskar 20e5f495d1SPrafulla Wadaskar /* 21e5f495d1SPrafulla Wadaskar * MFP configuration is represented by a 32-bit unsigned integer 22e5f495d1SPrafulla Wadaskar */ 23ee4303cfSXiang Wang #ifdef CONFIG_MVMFP_V2 24ee4303cfSXiang Wang #define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ 25ee4303cfSXiang Wang /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ 26ee4303cfSXiang Wang /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ 27ee4303cfSXiang Wang /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ 28ee4303cfSXiang Wang /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ 29ee4303cfSXiang Wang /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ 30ee4303cfSXiang Wang /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ 31ee4303cfSXiang Wang /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ 32ee4303cfSXiang Wang /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) 33ee4303cfSXiang Wang #else 34ee4303cfSXiang Wang #define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ 35e5f495d1SPrafulla Wadaskar /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ 36e5f495d1SPrafulla Wadaskar /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ 37e5f495d1SPrafulla Wadaskar /* bit 12 - Unused */ \ 38e5f495d1SPrafulla Wadaskar /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ 39ee4303cfSXiang Wang /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ 40e5f495d1SPrafulla Wadaskar /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ 41ee4303cfSXiang Wang /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ 42ee4303cfSXiang Wang /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) 43ee4303cfSXiang Wang #endif 44e5f495d1SPrafulla Wadaskar 45e5f495d1SPrafulla Wadaskar /* 46e5f495d1SPrafulla Wadaskar * to facilitate the definition, the following macros are provided 47e5f495d1SPrafulla Wadaskar * 48e5f495d1SPrafulla Wadaskar * offset, pull,pF, drv,dF, edge,eF ,afn,aF 49e5f495d1SPrafulla Wadaskar */ 50ee4303cfSXiang Wang #define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) 51ee4303cfSXiang Wang #define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) 52e5f495d1SPrafulla Wadaskar #define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) 53e5f495d1SPrafulla Wadaskar 54ee4303cfSXiang Wang #define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) 55ee4303cfSXiang Wang #define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) 56ee4303cfSXiang Wang #define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) 57ee4303cfSXiang Wang #define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) 58ee4303cfSXiang Wang #define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) 59ee4303cfSXiang Wang #define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) 60ee4303cfSXiang Wang #define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) 61ee4303cfSXiang Wang #define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) 62ee4303cfSXiang Wang #define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) 63e5f495d1SPrafulla Wadaskar 64ee4303cfSXiang Wang #define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) 65ee4303cfSXiang Wang #define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) 66ee4303cfSXiang Wang #define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) 67ee4303cfSXiang Wang #define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) 68ee4303cfSXiang Wang #define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) 69e5f495d1SPrafulla Wadaskar 70ee4303cfSXiang Wang #define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) 71ee4303cfSXiang Wang #define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) 72ee4303cfSXiang Wang #define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) 73ee4303cfSXiang Wang #define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) 74ee4303cfSXiang Wang #define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) 75e5f495d1SPrafulla Wadaskar 76ee4303cfSXiang Wang #define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) 77e5f495d1SPrafulla Wadaskar 78ee4303cfSXiang Wang #define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) 79ee4303cfSXiang Wang #define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) 80ee4303cfSXiang Wang #define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) 81ee4303cfSXiang Wang #define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) 82ee4303cfSXiang Wang #define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) 83e5f495d1SPrafulla Wadaskar 84ee4303cfSXiang Wang #define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) 85ee4303cfSXiang Wang #define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) 86ee4303cfSXiang Wang #define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) 87ee4303cfSXiang Wang #define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) 88ee4303cfSXiang Wang #define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) 89ee4303cfSXiang Wang #define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) 90ee4303cfSXiang Wang 91ee4303cfSXiang Wang #define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ 92ee4303cfSXiang Wang | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ 93ee4303cfSXiang Wang | MFP_AF_MASK) 94e5f495d1SPrafulla Wadaskar #define MFP_EOC 0xffffffff /* indicates end-of-conf */ 95e5f495d1SPrafulla Wadaskar 96e5f495d1SPrafulla Wadaskar /* Functions */ 97e5f495d1SPrafulla Wadaskar void mfp_config(u32 *mfp_cfgs); 98e5f495d1SPrafulla Wadaskar 99e5f495d1SPrafulla Wadaskar #endif /* __MVMFP_H */ 100