1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18 #ifndef __LINUX_MTD_NAND_H 19 #define __LINUX_MTD_NAND_H 20 21 #include "config.h" 22 23 #include "linux/mtd/compat.h" 24 #include "linux/mtd/mtd.h" 25 #include "linux/mtd/bbm.h" 26 27 28 struct mtd_info; 29 struct nand_flash_dev; 30 /* Scan and identify a NAND device */ 31 extern int nand_scan (struct mtd_info *mtd, int max_chips); 32 /* Separate phases of nand_scan(), allowing board driver to intervene 33 * and override command or ECC setup according to flash type */ 34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 const struct nand_flash_dev *table); 36 extern int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 extern void nand_release (struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 extern void nand_wait_ready(struct mtd_info *mtd); 43 44 /* This constant declares the max. oobsize / page, which 45 * is supported now. If you add a chip with bigger oobsize/page 46 * adjust this accordingly. 47 */ 48 #define NAND_MAX_OOBSIZE 218 49 #define NAND_MAX_PAGESIZE 4096 50 51 /* 52 * Constants for hardware specific CLE/ALE/NCE function 53 * 54 * These are bits which can be or'ed to set/clear multiple 55 * bits in one go. 56 */ 57 /* Select the chip by setting nCE to low */ 58 #define NAND_NCE 0x01 59 /* Select the command latch by setting CLE to high */ 60 #define NAND_CLE 0x02 61 /* Select the address latch by setting ALE to high */ 62 #define NAND_ALE 0x04 63 64 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 65 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 66 #define NAND_CTRL_CHANGE 0x80 67 68 /* 69 * Standard NAND flash commands 70 */ 71 #define NAND_CMD_READ0 0 72 #define NAND_CMD_READ1 1 73 #define NAND_CMD_RNDOUT 5 74 #define NAND_CMD_PAGEPROG 0x10 75 #define NAND_CMD_READOOB 0x50 76 #define NAND_CMD_ERASE1 0x60 77 #define NAND_CMD_STATUS 0x70 78 #define NAND_CMD_STATUS_MULTI 0x71 79 #define NAND_CMD_SEQIN 0x80 80 #define NAND_CMD_RNDIN 0x85 81 #define NAND_CMD_READID 0x90 82 #define NAND_CMD_PARAM 0xec 83 #define NAND_CMD_ERASE2 0xd0 84 #define NAND_CMD_RESET 0xff 85 86 /* Extended commands for large page devices */ 87 #define NAND_CMD_READSTART 0x30 88 #define NAND_CMD_RNDOUTSTART 0xE0 89 #define NAND_CMD_CACHEDPROG 0x15 90 91 /* Extended commands for AG-AND device */ 92 /* 93 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 94 * there is no way to distinguish that from NAND_CMD_READ0 95 * until the remaining sequence of commands has been completed 96 * so add a high order bit and mask it off in the command. 97 */ 98 #define NAND_CMD_DEPLETE1 0x100 99 #define NAND_CMD_DEPLETE2 0x38 100 #define NAND_CMD_STATUS_MULTI 0x71 101 #define NAND_CMD_STATUS_ERROR 0x72 102 /* multi-bank error status (banks 0-3) */ 103 #define NAND_CMD_STATUS_ERROR0 0x73 104 #define NAND_CMD_STATUS_ERROR1 0x74 105 #define NAND_CMD_STATUS_ERROR2 0x75 106 #define NAND_CMD_STATUS_ERROR3 0x76 107 #define NAND_CMD_STATUS_RESET 0x7f 108 #define NAND_CMD_STATUS_CLEAR 0xff 109 110 #define NAND_CMD_NONE -1 111 112 /* Status bits */ 113 #define NAND_STATUS_FAIL 0x01 114 #define NAND_STATUS_FAIL_N1 0x02 115 #define NAND_STATUS_TRUE_READY 0x20 116 #define NAND_STATUS_READY 0x40 117 #define NAND_STATUS_WP 0x80 118 119 /* 120 * Constants for ECC_MODES 121 */ 122 typedef enum { 123 NAND_ECC_NONE, 124 NAND_ECC_SOFT, 125 NAND_ECC_HW, 126 NAND_ECC_HW_SYNDROME, 127 NAND_ECC_HW_OOB_FIRST, 128 NAND_ECC_SOFT_BCH, 129 } nand_ecc_modes_t; 130 131 /* 132 * Constants for Hardware ECC 133 */ 134 /* Reset Hardware ECC for read */ 135 #define NAND_ECC_READ 0 136 /* Reset Hardware ECC for write */ 137 #define NAND_ECC_WRITE 1 138 /* Enable Hardware ECC before syndrom is read back from flash */ 139 #define NAND_ECC_READSYN 2 140 141 /* Bit mask for flags passed to do_nand_read_ecc */ 142 #define NAND_GET_DEVICE 0x80 143 144 145 /* Option constants for bizarre disfunctionality and real 146 * features 147 */ 148 /* Chip can not auto increment pages */ 149 #define NAND_NO_AUTOINCR 0x00000001 150 /* Buswitdh is 16 bit */ 151 #define NAND_BUSWIDTH_16 0x00000002 152 /* Device supports partial programming without padding */ 153 #define NAND_NO_PADDING 0x00000004 154 /* Chip has cache program function */ 155 #define NAND_CACHEPRG 0x00000008 156 /* Chip has copy back function */ 157 #define NAND_COPYBACK 0x00000010 158 /* AND Chip which has 4 banks and a confusing page / block 159 * assignment. See Renesas datasheet for further information */ 160 #define NAND_IS_AND 0x00000020 161 /* Chip has a array of 4 pages which can be read without 162 * additional ready /busy waits */ 163 #define NAND_4PAGE_ARRAY 0x00000040 164 /* Chip requires that BBT is periodically rewritten to prevent 165 * bits from adjacent blocks from 'leaking' in altering data. 166 * This happens with the Renesas AG-AND chips, possibly others. */ 167 #define BBT_AUTO_REFRESH 0x00000080 168 /* Chip does not require ready check on read. True 169 * for all large page devices, as they do not support 170 * autoincrement.*/ 171 #define NAND_NO_READRDY 0x00000100 172 /* Chip does not allow subpage writes */ 173 #define NAND_NO_SUBPAGE_WRITE 0x00000200 174 175 176 /* Options valid for Samsung large page devices */ 177 #define NAND_SAMSUNG_LP_OPTIONS \ 178 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 179 180 /* Macros to identify the above */ 181 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 182 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 183 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 184 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 185 /* Large page NAND with SOFT_ECC should support subpage reads */ 186 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 187 && (chip->page_shift > 9)) 188 189 /* Mask to zero out the chip options, which come from the id table */ 190 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 191 192 /* Non chip related options */ 193 /* Use a flash based bad block table. This option is passed to the 194 * default bad block table function. */ 195 #define NAND_USE_FLASH_BBT 0x00010000 196 /* This option skips the bbt scan during initialization. */ 197 #define NAND_SKIP_BBTSCAN 0x00020000 198 /* This option is defined if the board driver allocates its own buffers 199 (e.g. because it needs them DMA-coherent */ 200 #define NAND_OWN_BUFFERS 0x00040000 201 /* Options set by nand scan */ 202 /* bbt has already been read */ 203 #define NAND_BBT_SCANNED 0x40000000 204 /* Nand scan has allocated controller struct */ 205 #define NAND_CONTROLLER_ALLOC 0x80000000 206 207 /* Cell info constants */ 208 #define NAND_CI_CHIPNR_MSK 0x03 209 #define NAND_CI_CELLTYPE_MSK 0x0C 210 211 /* Keep gcc happy */ 212 struct nand_chip; 213 214 struct nand_onfi_params { 215 /* rev info and features block */ 216 /* 'O' 'N' 'F' 'I' */ 217 u8 sig[4]; 218 __le16 revision; 219 __le16 features; 220 __le16 opt_cmd; 221 u8 reserved[22]; 222 223 /* manufacturer information block */ 224 char manufacturer[12]; 225 char model[20]; 226 u8 jedec_id; 227 __le16 date_code; 228 u8 reserved2[13]; 229 230 /* memory organization block */ 231 __le32 byte_per_page; 232 __le16 spare_bytes_per_page; 233 __le32 data_bytes_per_ppage; 234 __le16 spare_bytes_per_ppage; 235 __le32 pages_per_block; 236 __le32 blocks_per_lun; 237 u8 lun_count; 238 u8 addr_cycles; 239 u8 bits_per_cell; 240 __le16 bb_per_lun; 241 __le16 block_endurance; 242 u8 guaranteed_good_blocks; 243 __le16 guaranteed_block_endurance; 244 u8 programs_per_page; 245 u8 ppage_attr; 246 u8 ecc_bits; 247 u8 interleaved_bits; 248 u8 interleaved_ops; 249 u8 reserved3[13]; 250 251 /* electrical parameter block */ 252 u8 io_pin_capacitance_max; 253 __le16 async_timing_mode; 254 __le16 program_cache_timing_mode; 255 __le16 t_prog; 256 __le16 t_bers; 257 __le16 t_r; 258 __le16 t_ccs; 259 __le16 src_sync_timing_mode; 260 __le16 src_ssync_features; 261 __le16 clk_pin_capacitance_typ; 262 __le16 io_pin_capacitance_typ; 263 __le16 input_pin_capacitance_typ; 264 u8 input_pin_capacitance_max; 265 u8 driver_strenght_support; 266 __le16 t_int_r; 267 __le16 t_ald; 268 u8 reserved4[7]; 269 270 /* vendor */ 271 u8 reserved5[90]; 272 273 __le16 crc; 274 } __attribute__((packed)); 275 276 #define ONFI_CRC_BASE 0x4F4E 277 278 279 /** 280 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 281 * @lock: protection lock 282 * @active: the mtd device which holds the controller currently 283 * @wq: wait queue to sleep on if a NAND operation is in progress 284 * used instead of the per chip wait queue when a hw controller is available 285 */ 286 struct nand_hw_control { 287 /* XXX U-BOOT XXX */ 288 #if 0 289 spinlock_t lock; 290 wait_queue_head_t wq; 291 #endif 292 struct nand_chip *active; 293 }; 294 295 /** 296 * struct nand_ecc_ctrl - Control structure for ecc 297 * @mode: ecc mode 298 * @steps: number of ecc steps per page 299 * @size: data bytes per ecc step 300 * @bytes: ecc bytes per step 301 * @total: total number of ecc bytes per page 302 * @prepad: padding information for syndrome based ecc generators 303 * @postpad: padding information for syndrome based ecc generators 304 * @layout: ECC layout control struct pointer 305 * @priv: pointer to private ecc control data 306 * @hwctl: function to control hardware ecc generator. Must only 307 * be provided if an hardware ECC is available 308 * @calculate: function for ecc calculation or readback from ecc hardware 309 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 310 * @read_page_raw: function to read a raw page without ECC 311 * @write_page_raw: function to write a raw page without ECC 312 * @read_page: function to read a page according to the ecc generator requirements 313 * @write_page: function to write a page according to the ecc generator requirements 314 * @read_oob: function to read chip OOB data 315 * @write_oob: function to write chip OOB data 316 */ 317 struct nand_ecc_ctrl { 318 nand_ecc_modes_t mode; 319 int steps; 320 int size; 321 int bytes; 322 int total; 323 int prepad; 324 int postpad; 325 struct nand_ecclayout *layout; 326 void *priv; 327 void (*hwctl)(struct mtd_info *mtd, int mode); 328 int (*calculate)(struct mtd_info *mtd, 329 const uint8_t *dat, 330 uint8_t *ecc_code); 331 int (*correct)(struct mtd_info *mtd, uint8_t *dat, 332 uint8_t *read_ecc, 333 uint8_t *calc_ecc); 334 int (*read_page_raw)(struct mtd_info *mtd, 335 struct nand_chip *chip, 336 uint8_t *buf, int page); 337 void (*write_page_raw)(struct mtd_info *mtd, 338 struct nand_chip *chip, 339 const uint8_t *buf); 340 int (*read_page)(struct mtd_info *mtd, 341 struct nand_chip *chip, 342 uint8_t *buf, int page); 343 int (*read_subpage)(struct mtd_info *mtd, 344 struct nand_chip *chip, 345 uint32_t offs, uint32_t len, 346 uint8_t *buf); 347 void (*write_page)(struct mtd_info *mtd, 348 struct nand_chip *chip, 349 const uint8_t *buf); 350 int (*read_oob)(struct mtd_info *mtd, 351 struct nand_chip *chip, 352 int page, 353 int sndcmd); 354 int (*write_oob)(struct mtd_info *mtd, 355 struct nand_chip *chip, 356 int page); 357 }; 358 359 /** 360 * struct nand_buffers - buffer structure for read/write 361 * @ecccalc: buffer for calculated ecc 362 * @ecccode: buffer for ecc read from flash 363 * @databuf: buffer for data - dynamically sized 364 * 365 * Do not change the order of buffers. databuf and oobrbuf must be in 366 * consecutive order. 367 */ 368 struct nand_buffers { 369 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 370 uint8_t ecccode[NAND_MAX_OOBSIZE]; 371 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 372 }; 373 374 /** 375 * struct nand_chip - NAND Private Flash Chip Data 376 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 377 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 378 * @read_byte: [REPLACEABLE] read one byte from the chip 379 * @read_word: [REPLACEABLE] read one word from the chip 380 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 381 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 382 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 383 * @select_chip: [REPLACEABLE] select chip nr 384 * @block_bad: [REPLACEABLE] check, if the block is bad 385 * @block_markbad: [REPLACEABLE] mark the block bad 386 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling 387 * ALE/CLE/nCE. Also used to write command and address 388 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 389 * If set to NULL no access to ready/busy is available and the ready/busy information 390 * is read from the chip status register 391 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 392 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 393 * @ecc: [BOARDSPECIFIC] ecc control ctructure 394 * @buffers: buffer structure for read/write 395 * @hwcontrol: platform-specific hardware control structure 396 * @ops: oob operation operands 397 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 398 * @scan_bbt: [REPLACEABLE] function to scan bad block table 399 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 400 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 401 * @state: [INTERN] the current state of the NAND device 402 * @oob_poi: poison value buffer 403 * @page_shift: [INTERN] number of address bits in a page (column address bits) 404 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 405 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 406 * @chip_shift: [INTERN] number of address bits in one chip 407 * @datbuf: [INTERN] internal buffer for one page + oob 408 * @oobbuf: [INTERN] oob buffer for one eraseblock 409 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 410 * @data_poi: [INTERN] pointer to a data buffer 411 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 412 * special functionality. See the defines for further explanation 413 * @badblockpos: [INTERN] position of the bad block marker in the oob area 414 * @cellinfo: [INTERN] MLC/multichip data from chip ident 415 * @numchips: [INTERN] number of physical chips 416 * @chipsize: [INTERN] the size of one chip for multichip arrays 417 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 418 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 419 * @subpagesize: [INTERN] holds the subpagesize 420 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 421 * @bbt: [INTERN] bad block table pointer 422 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 423 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 424 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 425 * @controller: [REPLACEABLE] a pointer to a hardware controller structure 426 * which is shared among multiple independend devices 427 * @priv: [OPTIONAL] pointer to private chip date 428 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 429 * (determine if errors are correctable) 430 * @write_page: [REPLACEABLE] High-level page write function 431 */ 432 433 struct nand_chip { 434 void __iomem *IO_ADDR_R; 435 void __iomem *IO_ADDR_W; 436 437 uint8_t (*read_byte)(struct mtd_info *mtd); 438 u16 (*read_word)(struct mtd_info *mtd); 439 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 440 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 441 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 442 void (*select_chip)(struct mtd_info *mtd, int chip); 443 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 444 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 445 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 446 unsigned int ctrl); 447 int (*dev_ready)(struct mtd_info *mtd); 448 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 449 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 450 void (*erase_cmd)(struct mtd_info *mtd, int page); 451 int (*scan_bbt)(struct mtd_info *mtd); 452 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); 453 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 454 const uint8_t *buf, int page, int cached, int raw); 455 456 int chip_delay; 457 unsigned int options; 458 459 int page_shift; 460 int phys_erase_shift; 461 int bbt_erase_shift; 462 int chip_shift; 463 int numchips; 464 uint64_t chipsize; 465 int pagemask; 466 int pagebuf; 467 int subpagesize; 468 uint8_t cellinfo; 469 int badblockpos; 470 int onfi_version; 471 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 472 struct nand_onfi_params onfi_params; 473 #endif 474 475 int state; 476 477 uint8_t *oob_poi; 478 struct nand_hw_control *controller; 479 struct nand_ecclayout *ecclayout; 480 481 struct nand_ecc_ctrl ecc; 482 struct nand_buffers *buffers; 483 484 struct nand_hw_control hwcontrol; 485 486 struct mtd_oob_ops ops; 487 488 uint8_t *bbt; 489 struct nand_bbt_descr *bbt_td; 490 struct nand_bbt_descr *bbt_md; 491 492 struct nand_bbt_descr *badblock_pattern; 493 494 void *priv; 495 }; 496 497 /* 498 * NAND Flash Manufacturer ID Codes 499 */ 500 #define NAND_MFR_TOSHIBA 0x98 501 #define NAND_MFR_SAMSUNG 0xec 502 #define NAND_MFR_FUJITSU 0x04 503 #define NAND_MFR_NATIONAL 0x8f 504 #define NAND_MFR_RENESAS 0x07 505 #define NAND_MFR_STMICRO 0x20 506 #define NAND_MFR_HYNIX 0xad 507 #define NAND_MFR_MICRON 0x2c 508 #define NAND_MFR_AMD 0x01 509 510 /** 511 * struct nand_flash_dev - NAND Flash Device ID Structure 512 * @name: Identify the device type 513 * @id: device ID code 514 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 515 * If the pagesize is 0, then the real pagesize 516 * and the eraseize are determined from the 517 * extended id bytes in the chip 518 * @erasesize: Size of an erase block in the flash device. 519 * @chipsize: Total chipsize in Mega Bytes 520 * @options: Bitfield to store chip relevant options 521 */ 522 struct nand_flash_dev { 523 char *name; 524 int id; 525 unsigned long pagesize; 526 unsigned long chipsize; 527 unsigned long erasesize; 528 unsigned long options; 529 }; 530 531 /** 532 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 533 * @name: Manufacturer name 534 * @id: manufacturer ID code of device. 535 */ 536 struct nand_manufacturers { 537 int id; 538 char * name; 539 }; 540 541 extern const struct nand_flash_dev nand_flash_ids[]; 542 extern const struct nand_manufacturers nand_manuf_ids[]; 543 544 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 545 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 546 extern int nand_default_bbt(struct mtd_info *mtd); 547 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 548 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 549 int allowbbt); 550 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 551 size_t * retlen, uint8_t * buf); 552 553 /* 554 * Constants for oob configuration 555 */ 556 #define NAND_SMALL_BADBLOCK_POS 5 557 #define NAND_LARGE_BADBLOCK_POS 0 558 559 /** 560 * struct platform_nand_chip - chip level device structure 561 * @nr_chips: max. number of chips to scan for 562 * @chip_offset: chip number offset 563 * @nr_partitions: number of partitions pointed to by partitions (or zero) 564 * @partitions: mtd partition list 565 * @chip_delay: R/B delay value in us 566 * @options: Option flags, e.g. 16bit buswidth 567 * @ecclayout: ecc layout info structure 568 * @part_probe_types: NULL-terminated array of probe types 569 * @priv: hardware controller specific settings 570 */ 571 struct platform_nand_chip { 572 int nr_chips; 573 int chip_offset; 574 int nr_partitions; 575 struct mtd_partition *partitions; 576 struct nand_ecclayout *ecclayout; 577 int chip_delay; 578 unsigned int options; 579 const char **part_probe_types; 580 void *priv; 581 }; 582 583 /** 584 * struct platform_nand_ctrl - controller level device structure 585 * @hwcontrol: platform specific hardware control structure 586 * @dev_ready: platform specific function to read ready/busy pin 587 * @select_chip: platform specific chip select function 588 * @cmd_ctrl: platform specific function for controlling 589 * ALE/CLE/nCE. Also used to write command and address 590 * @priv: private data to transport driver specific settings 591 * 592 * All fields are optional and depend on the hardware driver requirements 593 */ 594 struct platform_nand_ctrl { 595 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 596 int (*dev_ready)(struct mtd_info *mtd); 597 void (*select_chip)(struct mtd_info *mtd, int chip); 598 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 599 unsigned int ctrl); 600 void *priv; 601 }; 602 603 /** 604 * struct platform_nand_data - container structure for platform-specific data 605 * @chip: chip level chip structure 606 * @ctrl: controller level device structure 607 */ 608 struct platform_nand_data { 609 struct platform_nand_chip chip; 610 struct platform_nand_ctrl ctrl; 611 }; 612 613 /* Some helpers to access the data structures */ 614 static inline 615 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 616 { 617 struct nand_chip *chip = mtd->priv; 618 619 return chip->priv; 620 } 621 622 /* Standard NAND functions from nand_base.c */ 623 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 624 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 625 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 626 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 627 uint8_t nand_read_byte(struct mtd_info *mtd); 628 629 #endif /* __LINUX_MTD_NAND_H */ 630