1*4248acf6Swdenk /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 2*4248acf6Swdenk * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 3*4248acf6Swdenk * derived from Data Sheet, Copyright Motorola 1984 (!). 4*4248acf6Swdenk * It was written to be part of the Linux operating system. 5*4248acf6Swdenk */ 6*4248acf6Swdenk /* permission is hereby granted to copy, modify and redistribute this code 7*4248acf6Swdenk * in terms of the GNU Library General Public License, Version 2 or later, 8*4248acf6Swdenk * at your option. 9*4248acf6Swdenk */ 10*4248acf6Swdenk 11*4248acf6Swdenk #ifndef _MC146818RTC_H 12*4248acf6Swdenk #define _MC146818RTC_H 13*4248acf6Swdenk 14*4248acf6Swdenk #include <asm/io.h> 15*4248acf6Swdenk #include <linux/rtc.h> /* get the user-level API */ 16*4248acf6Swdenk #include <asm/mc146818rtc.h> /* register access macros */ 17*4248acf6Swdenk 18*4248acf6Swdenk /********************************************************************** 19*4248acf6Swdenk * register summary 20*4248acf6Swdenk **********************************************************************/ 21*4248acf6Swdenk #define RTC_SECONDS 0 22*4248acf6Swdenk #define RTC_SECONDS_ALARM 1 23*4248acf6Swdenk #define RTC_MINUTES 2 24*4248acf6Swdenk #define RTC_MINUTES_ALARM 3 25*4248acf6Swdenk #define RTC_HOURS 4 26*4248acf6Swdenk #define RTC_HOURS_ALARM 5 27*4248acf6Swdenk /* RTC_*_alarm is always true if 2 MSBs are set */ 28*4248acf6Swdenk # define RTC_ALARM_DONT_CARE 0xC0 29*4248acf6Swdenk 30*4248acf6Swdenk #define RTC_DAY_OF_WEEK 6 31*4248acf6Swdenk #define RTC_DAY_OF_MONTH 7 32*4248acf6Swdenk #define RTC_MONTH 8 33*4248acf6Swdenk #define RTC_YEAR 9 34*4248acf6Swdenk 35*4248acf6Swdenk /* control registers - Moto names 36*4248acf6Swdenk */ 37*4248acf6Swdenk #define RTC_REG_A 10 38*4248acf6Swdenk #define RTC_REG_B 11 39*4248acf6Swdenk #define RTC_REG_C 12 40*4248acf6Swdenk #define RTC_REG_D 13 41*4248acf6Swdenk 42*4248acf6Swdenk /********************************************************************** 43*4248acf6Swdenk * register details 44*4248acf6Swdenk **********************************************************************/ 45*4248acf6Swdenk #define RTC_FREQ_SELECT RTC_REG_A 46*4248acf6Swdenk 47*4248acf6Swdenk /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 48*4248acf6Swdenk * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 49*4248acf6Swdenk * totalling to a max high interval of 2.228 ms. 50*4248acf6Swdenk */ 51*4248acf6Swdenk # define RTC_UIP 0x80 52*4248acf6Swdenk # define RTC_DIV_CTL 0x70 53*4248acf6Swdenk /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 54*4248acf6Swdenk # define RTC_REF_CLCK_4MHZ 0x00 55*4248acf6Swdenk # define RTC_REF_CLCK_1MHZ 0x10 56*4248acf6Swdenk # define RTC_REF_CLCK_32KHZ 0x20 57*4248acf6Swdenk /* 2 values for divider stage reset, others for "testing purposes only" */ 58*4248acf6Swdenk # define RTC_DIV_RESET1 0x60 59*4248acf6Swdenk # define RTC_DIV_RESET2 0x70 60*4248acf6Swdenk /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 61*4248acf6Swdenk # define RTC_RATE_SELECT 0x0F 62*4248acf6Swdenk 63*4248acf6Swdenk /**********************************************************************/ 64*4248acf6Swdenk #define RTC_CONTROL RTC_REG_B 65*4248acf6Swdenk # define RTC_SET 0x80 /* disable updates for clock setting */ 66*4248acf6Swdenk # define RTC_PIE 0x40 /* periodic interrupt enable */ 67*4248acf6Swdenk # define RTC_AIE 0x20 /* alarm interrupt enable */ 68*4248acf6Swdenk # define RTC_UIE 0x10 /* update-finished interrupt enable */ 69*4248acf6Swdenk # define RTC_SQWE 0x08 /* enable square-wave output */ 70*4248acf6Swdenk # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 71*4248acf6Swdenk # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 72*4248acf6Swdenk # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 73*4248acf6Swdenk 74*4248acf6Swdenk /**********************************************************************/ 75*4248acf6Swdenk #define RTC_INTR_FLAGS RTC_REG_C 76*4248acf6Swdenk /* caution - cleared by read */ 77*4248acf6Swdenk # define RTC_IRQF 0x80 /* any of the following 3 is active */ 78*4248acf6Swdenk # define RTC_PF 0x40 79*4248acf6Swdenk # define RTC_AF 0x20 80*4248acf6Swdenk # define RTC_UF 0x10 81*4248acf6Swdenk 82*4248acf6Swdenk /**********************************************************************/ 83*4248acf6Swdenk #define RTC_VALID RTC_REG_D 84*4248acf6Swdenk # define RTC_VRT 0x80 /* valid RAM and time */ 85*4248acf6Swdenk /**********************************************************************/ 86*4248acf6Swdenk #endif /* _MC146818RTC_H */ 87