1*24c04977SStefan Roese /* 2*24c04977SStefan Roese * Marvell MBUS common definitions. 3*24c04977SStefan Roese * 4*24c04977SStefan Roese * Copyright (C) 2008 Marvell Semiconductor 5*24c04977SStefan Roese * 6*24c04977SStefan Roese * This file is licensed under the terms of the GNU General Public 7*24c04977SStefan Roese * License version 2. This program is licensed "as is" without any 8*24c04977SStefan Roese * warranty of any kind, whether express or implied. 9*24c04977SStefan Roese */ 10*24c04977SStefan Roese 11*24c04977SStefan Roese #ifndef __LINUX_MBUS_H 12*24c04977SStefan Roese #define __LINUX_MBUS_H 13*24c04977SStefan Roese 14*24c04977SStefan Roese struct resource; 15*24c04977SStefan Roese 16*24c04977SStefan Roese struct mbus_dram_target_info { 17*24c04977SStefan Roese /* 18*24c04977SStefan Roese * The 4-bit MBUS target ID of the DRAM controller. 19*24c04977SStefan Roese */ 20*24c04977SStefan Roese u8 mbus_dram_target_id; 21*24c04977SStefan Roese 22*24c04977SStefan Roese /* 23*24c04977SStefan Roese * The base address, size, and MBUS attribute ID for each 24*24c04977SStefan Roese * of the possible DRAM chip selects. Peripherals are 25*24c04977SStefan Roese * required to support at least 4 decode windows. 26*24c04977SStefan Roese */ 27*24c04977SStefan Roese int num_cs; 28*24c04977SStefan Roese struct mbus_dram_window { 29*24c04977SStefan Roese u8 cs_index; 30*24c04977SStefan Roese u8 mbus_attr; 31*24c04977SStefan Roese u32 base; 32*24c04977SStefan Roese u32 size; 33*24c04977SStefan Roese } cs[4]; 34*24c04977SStefan Roese }; 35*24c04977SStefan Roese 36*24c04977SStefan Roese struct mvebu_mbus_state { 37*24c04977SStefan Roese void __iomem *mbuswins_base; 38*24c04977SStefan Roese void __iomem *sdramwins_base; 39*24c04977SStefan Roese struct dentry *debugfs_root; 40*24c04977SStefan Roese struct dentry *debugfs_sdram; 41*24c04977SStefan Roese struct dentry *debugfs_devs; 42*24c04977SStefan Roese const struct mvebu_mbus_soc_data *soc; 43*24c04977SStefan Roese int hw_io_coherency; 44*24c04977SStefan Roese }; 45*24c04977SStefan Roese 46*24c04977SStefan Roese /* Flags for PCI/PCIe address decoding regions */ 47*24c04977SStefan Roese #define MVEBU_MBUS_PCI_IO 0x1 48*24c04977SStefan Roese #define MVEBU_MBUS_PCI_MEM 0x2 49*24c04977SStefan Roese #define MVEBU_MBUS_PCI_WA 0x3 50*24c04977SStefan Roese 51*24c04977SStefan Roese /* 52*24c04977SStefan Roese * Magic value that explicits that we don't need a remapping-capable 53*24c04977SStefan Roese * address decoding window. 54*24c04977SStefan Roese */ 55*24c04977SStefan Roese #define MVEBU_MBUS_NO_REMAP (0xffffffff) 56*24c04977SStefan Roese 57*24c04977SStefan Roese /* Maximum size of a mbus window name */ 58*24c04977SStefan Roese #define MVEBU_MBUS_MAX_WINNAME_SZ 32 59*24c04977SStefan Roese 60*24c04977SStefan Roese const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); 61*24c04977SStefan Roese void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); 62*24c04977SStefan Roese void mvebu_mbus_get_pcie_io_aperture(struct resource *res); 63*24c04977SStefan Roese int mvebu_mbus_add_window_remap_by_id(unsigned int target, 64*24c04977SStefan Roese unsigned int attribute, 65*24c04977SStefan Roese phys_addr_t base, size_t size, 66*24c04977SStefan Roese phys_addr_t remap); 67*24c04977SStefan Roese int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, 68*24c04977SStefan Roese phys_addr_t base, size_t size); 69*24c04977SStefan Roese int mvebu_mbus_del_window(phys_addr_t base, size_t size); 70*24c04977SStefan Roese int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, 71*24c04977SStefan Roese u32 base, u32 size, u8 target, u8 attr); 72*24c04977SStefan Roese 73*24c04977SStefan Roese #endif /* __LINUX_MBUS_H */ 74