1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2063c1263SAndy Fleming /* 35be00a01SClaudiu Manoil * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. 4063c1263SAndy Fleming * Jun-jie Zhang <b18070@freescale.com> 5063c1263SAndy Fleming * Mingkai Hu <Mingkai.hu@freescale.com> 6063c1263SAndy Fleming */ 79872b736SBin Meng 8063c1263SAndy Fleming #ifndef __FSL_PHY_H__ 9063c1263SAndy Fleming #define __FSL_PHY_H__ 10063c1263SAndy Fleming 11063c1263SAndy Fleming #include <net.h> 12063c1263SAndy Fleming #include <miiphy.h> 1393f26f13SClaudiu Manoil 1493f26f13SClaudiu Manoil struct tsec_mii_mng { 1593f26f13SClaudiu Manoil u32 miimcfg; /* MII management configuration reg */ 1693f26f13SClaudiu Manoil u32 miimcom; /* MII management command reg */ 1793f26f13SClaudiu Manoil u32 miimadd; /* MII management address reg */ 1893f26f13SClaudiu Manoil u32 miimcon; /* MII management control reg */ 1993f26f13SClaudiu Manoil u32 miimstat; /* MII management status reg */ 2093f26f13SClaudiu Manoil u32 miimind; /* MII management indication reg */ 2193f26f13SClaudiu Manoil u32 ifstat; /* Interface Status Register */ 2293f26f13SClaudiu Manoil }; 2393f26f13SClaudiu Manoil 2493f26f13SClaudiu Manoil int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); 25063c1263SAndy Fleming 26063c1263SAndy Fleming /* PHY register offsets */ 27063c1263SAndy Fleming #define PHY_EXT_PAGE_ACCESS 0x1f 28063c1263SAndy Fleming 29063c1263SAndy Fleming /* MII Management Configuration Register */ 30063c1263SAndy Fleming #define MIIMCFG_RESET_MGMT 0x80000000 31063c1263SAndy Fleming #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 32063c1263SAndy Fleming #define MIIMCFG_INIT_VALUE 0x00000003 33063c1263SAndy Fleming 34063c1263SAndy Fleming /* MII Management Command Register */ 35063c1263SAndy Fleming #define MIIMCOM_READ_CYCLE 0x00000001 36063c1263SAndy Fleming #define MIIMCOM_SCAN_CYCLE 0x00000002 37063c1263SAndy Fleming 38063c1263SAndy Fleming /* MII Management Address Register */ 39063c1263SAndy Fleming #define MIIMADD_PHY_ADDR_SHIFT 8 40063c1263SAndy Fleming 41063c1263SAndy Fleming /* MII Management Indicator Register */ 42063c1263SAndy Fleming #define MIIMIND_BUSY 0x00000001 43063c1263SAndy Fleming #define MIIMIND_NOTVALID 0x00000004 44063c1263SAndy Fleming 455be00a01SClaudiu Manoil void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, 46063c1263SAndy Fleming int dev_addr, int reg, int value); 475be00a01SClaudiu Manoil int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, 48063c1263SAndy Fleming int dev_addr, int regnum); 49063c1263SAndy Fleming int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); 50063c1263SAndy Fleming int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, 51063c1263SAndy Fleming u16 value); 52111fd19eSRoy Zang int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 53111fd19eSRoy Zang int regnum, u16 value); 54111fd19eSRoy Zang int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 55111fd19eSRoy Zang int regnum); 56063c1263SAndy Fleming 57063c1263SAndy Fleming struct fsl_pq_mdio_info { 585be00a01SClaudiu Manoil struct tsec_mii_mng __iomem *regs; 59063c1263SAndy Fleming char *name; 60063c1263SAndy Fleming }; 61063c1263SAndy Fleming int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); 62063c1263SAndy Fleming 63063c1263SAndy Fleming #endif /* __FSL_PHY_H__ */ 64