1024a26bcSwdenk /* 2024a26bcSwdenk * (C) Copyright 2002 3024a26bcSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4024a26bcSwdenk * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6024a26bcSwdenk */ 7024a26bcSwdenk 8024a26bcSwdenk #include <linux/types.h> /* for ulong typedef */ 9024a26bcSwdenk 10024a26bcSwdenk #ifndef _FPGA_H_ 11024a26bcSwdenk #define _FPGA_H_ 12024a26bcSwdenk 13024a26bcSwdenk #ifndef CONFIG_MAX_FPGA_DEVICES 14024a26bcSwdenk #define CONFIG_MAX_FPGA_DEVICES 5 15024a26bcSwdenk #endif 16024a26bcSwdenk 17024a26bcSwdenk /* fpga_xxxx function return value definitions */ 18024a26bcSwdenk #define FPGA_SUCCESS 0 19024a26bcSwdenk #define FPGA_FAIL -1 20024a26bcSwdenk 21024a26bcSwdenk /* device numbers must be non-negative */ 22024a26bcSwdenk #define FPGA_INVALID_DEVICE -1 23024a26bcSwdenk 24024a26bcSwdenk /* root data type defintions */ 25024a26bcSwdenk typedef enum { /* typedef fpga_type */ 26024a26bcSwdenk fpga_min_type, /* range check value */ 27024a26bcSwdenk fpga_xilinx, /* Xilinx Family) */ 28024a26bcSwdenk fpga_altera, /* unimplemented */ 293b8ac464SStefano Babic fpga_lattice, /* Lattice family */ 30024a26bcSwdenk fpga_undefined /* invalid range check value */ 31024a26bcSwdenk } fpga_type; /* end, typedef fpga_type */ 32024a26bcSwdenk 33024a26bcSwdenk typedef struct { /* typedef fpga_desc */ 34024a26bcSwdenk fpga_type devtype; /* switch value to select sub-functions */ 35024a26bcSwdenk void *devdesc; /* real device descriptor */ 36024a26bcSwdenk } fpga_desc; /* end, typedef fpga_desc */ 37024a26bcSwdenk 381a897668SSiva Durga Prasad Paladugu typedef struct { /* typedef fpga_desc */ 391a897668SSiva Durga Prasad Paladugu unsigned int blocksize; 401a897668SSiva Durga Prasad Paladugu char *interface; 411a897668SSiva Durga Prasad Paladugu char *dev_part; 421a897668SSiva Durga Prasad Paladugu char *filename; 431a897668SSiva Durga Prasad Paladugu int fstype; 441a897668SSiva Durga Prasad Paladugu } fpga_fs_info; 45024a26bcSwdenk 467a78bd26SMichal Simek typedef enum { 477a78bd26SMichal Simek BIT_FULL = 0, 4867193864SMichal Simek BIT_PARTIAL, 497a78bd26SMichal Simek } bitstream_type; 507a78bd26SMichal Simek 51024a26bcSwdenk /* root function definitions */ 52*6583505cSMichal Simek void fpga_init(void); 53*6583505cSMichal Simek int fpga_add(fpga_type devtype, void *desc); 54*6583505cSMichal Simek int fpga_count(void); 55*6583505cSMichal Simek int fpga_load(int devnum, const void *buf, size_t bsize, 567a78bd26SMichal Simek bitstream_type bstype); 57*6583505cSMichal Simek int fpga_fsload(int devnum, const void *buf, size_t size, 581a897668SSiva Durga Prasad Paladugu fpga_fs_info *fpga_fsinfo); 59*6583505cSMichal Simek int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 607a78bd26SMichal Simek bitstream_type bstype); 61*6583505cSMichal Simek int fpga_dump(int devnum, const void *buf, size_t bsize); 62*6583505cSMichal Simek int fpga_info(int devnum); 63*6583505cSMichal Simek const fpga_desc *const fpga_validate(int devnum, const void *buf, 646631db47SMichal Simek size_t bsize, char *fn); 65024a26bcSwdenk 66024a26bcSwdenk #endif /* _FPGA_H_ */ 67