1*024a26bcSwdenk /* 2*024a26bcSwdenk * (C) Copyright 2002 3*024a26bcSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*024a26bcSwdenk * 5*024a26bcSwdenk * See file CREDITS for list of people who contributed to this 6*024a26bcSwdenk * project. 7*024a26bcSwdenk * 8*024a26bcSwdenk * This program is free software; you can redistribute it and/or 9*024a26bcSwdenk * modify it under the terms of the GNU General Public License as 10*024a26bcSwdenk * published by the Free Software Foundation; either version 2 of 11*024a26bcSwdenk * the License, or (at your option) any later version. 12*024a26bcSwdenk * 13*024a26bcSwdenk * This program is distributed in the hope that it will be useful, 14*024a26bcSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*024a26bcSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*024a26bcSwdenk * GNU General Public License for more details. 17*024a26bcSwdenk * 18*024a26bcSwdenk * You should have received a copy of the GNU General Public License 19*024a26bcSwdenk * along with this program; if not, write to the Free Software 20*024a26bcSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*024a26bcSwdenk * MA 02111-1307 USA 22*024a26bcSwdenk * 23*024a26bcSwdenk */ 24*024a26bcSwdenk 25*024a26bcSwdenk #include <linux/types.h> /* for ulong typedef */ 26*024a26bcSwdenk 27*024a26bcSwdenk #ifndef _FPGA_H_ 28*024a26bcSwdenk #define _FPGA_H_ 29*024a26bcSwdenk 30*024a26bcSwdenk #ifndef CONFIG_MAX_FPGA_DEVICES 31*024a26bcSwdenk #define CONFIG_MAX_FPGA_DEVICES 5 32*024a26bcSwdenk #endif 33*024a26bcSwdenk 34*024a26bcSwdenk /* these probably belong somewhere else */ 35*024a26bcSwdenk #ifndef FALSE 36*024a26bcSwdenk #define FALSE (0) 37*024a26bcSwdenk #endif 38*024a26bcSwdenk #ifndef TRUE 39*024a26bcSwdenk #define TRUE (!FALSE) 40*024a26bcSwdenk #endif 41*024a26bcSwdenk 42*024a26bcSwdenk /* CONFIG_FPGA bit assignments */ 43*024a26bcSwdenk #define CFG_FPGA_MAN(x) (x) 44*024a26bcSwdenk #define CFG_FPGA_DEV(x) ((x) << 8 ) 45*024a26bcSwdenk #define CFG_FPGA_IF(x) ((x) << 16 ) 46*024a26bcSwdenk 47*024a26bcSwdenk /* FPGA Manufacturer bits in CONFIG_FPGA */ 48*024a26bcSwdenk #define CFG_FPGA_XILINX CFG_FPGA_MAN( 0x1 ) 49*024a26bcSwdenk #define CFG_FPGA_ALTERA CFG_FPGA_MAN( 0x2 ) 50*024a26bcSwdenk 51*024a26bcSwdenk 52*024a26bcSwdenk /* fpga_xxxx function return value definitions */ 53*024a26bcSwdenk #define FPGA_SUCCESS 0 54*024a26bcSwdenk #define FPGA_FAIL -1 55*024a26bcSwdenk 56*024a26bcSwdenk /* device numbers must be non-negative */ 57*024a26bcSwdenk #define FPGA_INVALID_DEVICE -1 58*024a26bcSwdenk 59*024a26bcSwdenk /* root data type defintions */ 60*024a26bcSwdenk typedef enum { /* typedef fpga_type */ 61*024a26bcSwdenk fpga_min_type, /* range check value */ 62*024a26bcSwdenk fpga_xilinx, /* Xilinx Family) */ 63*024a26bcSwdenk fpga_altera, /* unimplemented */ 64*024a26bcSwdenk fpga_undefined /* invalid range check value */ 65*024a26bcSwdenk } fpga_type; /* end, typedef fpga_type */ 66*024a26bcSwdenk 67*024a26bcSwdenk typedef struct { /* typedef fpga_desc */ 68*024a26bcSwdenk fpga_type devtype; /* switch value to select sub-functions */ 69*024a26bcSwdenk void * devdesc; /* real device descriptor */ 70*024a26bcSwdenk } fpga_desc; /* end, typedef fpga_desc */ 71*024a26bcSwdenk 72*024a26bcSwdenk 73*024a26bcSwdenk /* root function definitions */ 74*024a26bcSwdenk extern void fpga_init( ulong reloc_off ); 75*024a26bcSwdenk extern int fpga_add( fpga_type devtype, void *desc ); 76*024a26bcSwdenk extern const int fpga_count( void ); 77*024a26bcSwdenk extern int fpga_load( int devnum, void *buf, size_t bsize ); 78*024a26bcSwdenk extern int fpga_dump( int devnum, void *buf, size_t bsize ); 79*024a26bcSwdenk extern int fpga_info( int devnum ); 80*024a26bcSwdenk 81*024a26bcSwdenk #endif /* _FPGA_H_ */ 82