1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cbfa67a1SMarcel Ziswiler /* 3cbfa67a1SMarcel Ziswiler * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> 4cbfa67a1SMarcel Ziswiler */ 5cbfa67a1SMarcel Ziswiler 6cbfa67a1SMarcel Ziswiler #ifndef __SERIAL_PXA_H 7cbfa67a1SMarcel Ziswiler #define __SERIAL_PXA_H 8cbfa67a1SMarcel Ziswiler 9cbfa67a1SMarcel Ziswiler /* 10cbfa67a1SMarcel Ziswiler * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can 11cbfa67a1SMarcel Ziswiler * easily handle enabling of clock. 12cbfa67a1SMarcel Ziswiler */ 13cbfa67a1SMarcel Ziswiler #ifdef CONFIG_CPU_MONAHANS 14cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE CKENA_21_BTUART 15cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKENA 16cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 0 17cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 1 18cbfa67a1SMarcel Ziswiler #define STUART_INDEX 2 19cbfa67a1SMarcel Ziswiler #elif CONFIG_CPU_PXA25X 20cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE (1 << 4) /* HWUART */ 21cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKEN 22cbfa67a1SMarcel Ziswiler #define HWUART_INDEX 0 23cbfa67a1SMarcel Ziswiler #define STUART_INDEX 1 24cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 2 25cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 3 26cbfa67a1SMarcel Ziswiler #else /* PXA27x */ 27cbfa67a1SMarcel Ziswiler #define UART_CLK_BASE CKEN5_STUART 28cbfa67a1SMarcel Ziswiler #define UART_CLK_REG CKEN 29cbfa67a1SMarcel Ziswiler #define STUART_INDEX 0 30cbfa67a1SMarcel Ziswiler #define FFUART_INDEX 1 31cbfa67a1SMarcel Ziswiler #define BTUART_INDEX 2 32cbfa67a1SMarcel Ziswiler #endif 33cbfa67a1SMarcel Ziswiler 34cbfa67a1SMarcel Ziswiler /* 35cbfa67a1SMarcel Ziswiler * Only PXA250 has HWUART, to avoid poluting the code with more macros, 36cbfa67a1SMarcel Ziswiler * artificially introduce this. 37cbfa67a1SMarcel Ziswiler */ 38cbfa67a1SMarcel Ziswiler #ifndef CONFIG_CPU_PXA25X 39cbfa67a1SMarcel Ziswiler #define HWUART_INDEX 0xff 40cbfa67a1SMarcel Ziswiler #endif 41cbfa67a1SMarcel Ziswiler 42cbfa67a1SMarcel Ziswiler /* 43cbfa67a1SMarcel Ziswiler * struct pxa_serial_platdata - information about a PXA port 44cbfa67a1SMarcel Ziswiler * 45cbfa67a1SMarcel Ziswiler * @base: Uart port base register address 46cbfa67a1SMarcel Ziswiler * @port: Uart port index, for cpu with pinmux for uart / gpio 47cbfa67a1SMarcel Ziswiler * baudrtatre: Uart port baudrate 48cbfa67a1SMarcel Ziswiler */ 49cbfa67a1SMarcel Ziswiler struct pxa_serial_platdata { 50cbfa67a1SMarcel Ziswiler struct pxa_uart_regs *base; 51cbfa67a1SMarcel Ziswiler int port; 52cbfa67a1SMarcel Ziswiler int baudrate; 53cbfa67a1SMarcel Ziswiler }; 54cbfa67a1SMarcel Ziswiler 55cbfa67a1SMarcel Ziswiler #endif /* __SERIAL_PXA_H */ 56