1*1d6c54ecSMichal Simek /* SPDX-License-Identifier: GPL-2.0 */ 2*1d6c54ecSMichal Simek /* 3*1d6c54ecSMichal Simek * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) 4*1d6c54ecSMichal Simek */ 5*1d6c54ecSMichal Simek 6*1d6c54ecSMichal Simek #ifndef __CONFIG_ZYNQMP_R5_H 7*1d6c54ecSMichal Simek #define __CONFIG_ZYNQMP_R5_H 8*1d6c54ecSMichal Simek 9*1d6c54ecSMichal Simek #define CONFIG_EXTRA_ENV_SETTINGS 10*1d6c54ecSMichal Simek 11*1d6c54ecSMichal Simek /* CPU clock */ 12*1d6c54ecSMichal Simek #define CONFIG_CPU_FREQ_HZ 500000000 13*1d6c54ecSMichal Simek 14*1d6c54ecSMichal Simek /* Serial drivers */ 15*1d6c54ecSMichal Simek /* The following table includes the supported baudrates */ 16*1d6c54ecSMichal Simek #define CONFIG_SYS_BAUDRATE_TABLE \ 17*1d6c54ecSMichal Simek {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 18*1d6c54ecSMichal Simek 19*1d6c54ecSMichal Simek # define CONFIG_ENV_SIZE (128 << 10) 20*1d6c54ecSMichal Simek 21*1d6c54ecSMichal Simek /* Allow to overwrite serial and ethaddr */ 22*1d6c54ecSMichal Simek #define CONFIG_ENV_OVERWRITE 23*1d6c54ecSMichal Simek 24*1d6c54ecSMichal Simek /* Boot configuration */ 25*1d6c54ecSMichal Simek #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ 26*1d6c54ecSMichal Simek 27*1d6c54ecSMichal Simek #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 28*1d6c54ecSMichal Simek 29*1d6c54ecSMichal Simek #define CONFIG_SYS_MALLOC_LEN 0x1400000 30*1d6c54ecSMichal Simek 31*1d6c54ecSMichal Simek #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 32*1d6c54ecSMichal Simek #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 33*1d6c54ecSMichal Simek #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 34*1d6c54ecSMichal Simek CONFIG_SYS_INIT_RAM_SIZE - \ 35*1d6c54ecSMichal Simek GENERATED_GBL_DATA_SIZE) 36*1d6c54ecSMichal Simek 37*1d6c54ecSMichal Simek /* Extend size of kernel image for uncompression */ 38*1d6c54ecSMichal Simek #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) 39*1d6c54ecSMichal Simek 40*1d6c54ecSMichal Simek #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 41*1d6c54ecSMichal Simek 42*1d6c54ecSMichal Simek #define CONFIG_SKIP_LOWLEVEL_INIT 43*1d6c54ecSMichal Simek 44*1d6c54ecSMichal Simek /* 0x0 - 0x40 is used for placing exception vectors */ 45*1d6c54ecSMichal Simek #define CONFIG_SYS_MEMTEST_START 0x40 46*1d6c54ecSMichal Simek #define CONFIG_SYS_MEMTEST_END 0x100 47*1d6c54ecSMichal Simek #define CONFIG_SYS_MEMTEST_SCRATCH 0 48*1d6c54ecSMichal Simek 49*1d6c54ecSMichal Simek #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ 50