1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c8a6badeSSiva Durga Prasad Paladugu /* 3c8a6badeSSiva Durga Prasad Paladugu * Configuration for Xilinx ZynqMP Nand Flash utility 4c8a6badeSSiva Durga Prasad Paladugu * 5c8a6badeSSiva Durga Prasad Paladugu * (C) Copyright 2018 Xilinx, Inc. 6c8a6badeSSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 7c8a6badeSSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 8c8a6badeSSiva Durga Prasad Paladugu */ 9c8a6badeSSiva Durga Prasad Paladugu 10c8a6badeSSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_MINI_NAND_H 11c8a6badeSSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_MINI_NAND_H 12c8a6badeSSiva Durga Prasad Paladugu 13c8a6badeSSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp_mini.h> 14c8a6badeSSiva Durga Prasad Paladugu 15c8a6badeSSiva Durga Prasad Paladugu #define CONFIG_SYS_ICACHE_OFF 16c8a6badeSSiva Durga Prasad Paladugu #define CONFIG_SYS_SDRAM_SIZE 0x1000000 17c8a6badeSSiva Durga Prasad Paladugu #define CONFIG_SYS_SDRAM_BASE 0x0 18c8a6badeSSiva Durga Prasad Paladugu #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) 19c8a6badeSSiva Durga Prasad Paladugu #define CONFIG_SYS_MALLOC_LEN 0x800000 20c8a6badeSSiva Durga Prasad Paladugu 21c8a6badeSSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ 22