1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* U-Boot - Common settings for UniPhier Family */ 10 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__ 13 14 #define CONFIG_ARMV7_PSCI_1_0 15 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 17 18 #define CONFIG_SMC911X 19 20 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 21 #define CONFIG_SMC911X_BASE 0 22 #define CONFIG_SMC911X_32_BIT 23 24 /*----------------------------------------------------------------------- 25 * MMU and Cache Setting 26 *----------------------------------------------------------------------*/ 27 28 /* Comment out the following to enable L1 cache */ 29 /* #define CONFIG_SYS_ICACHE_OFF */ 30 /* #define CONFIG_SYS_DCACHE_OFF */ 31 32 #define CONFIG_DISPLAY_CPUINFO 33 #define CONFIG_DISPLAY_BOARDINFO 34 #define CONFIG_MISC_INIT_F 35 #define CONFIG_BOARD_EARLY_INIT_F 36 #define CONFIG_BOARD_EARLY_INIT_R 37 #define CONFIG_BOARD_LATE_INIT 38 39 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 40 41 #define CONFIG_TIMESTAMP 42 43 /* FLASH related */ 44 #define CONFIG_MTD_DEVICE 45 46 /* 47 * uncomment the following to disable FLASH related code. 48 */ 49 /* #define CONFIG_SYS_NO_FLASH */ 50 51 #define CONFIG_FLASH_CFI_DRIVER 52 #define CONFIG_SYS_FLASH_CFI 53 54 #define CONFIG_SYS_MAX_FLASH_SECT 256 55 #define CONFIG_SYS_MONITOR_BASE 0 56 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 57 #define CONFIG_SYS_FLASH_BASE 0 58 59 /* 60 * flash_toggle does not work for out supoort card. 61 * We need to use flash_status_poll. 62 */ 63 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 64 65 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 66 67 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 68 69 /* serial console configuration */ 70 #define CONFIG_BAUDRATE 115200 71 72 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 73 #define CONFIG_USE_ARCH_MEMSET 74 #define CONFIG_USE_ARCH_MEMCPY 75 #endif 76 77 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 78 79 #define CONFIG_CMDLINE_EDITING /* add command line history */ 80 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 81 /* Print Buffer Size */ 82 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 83 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 84 /* Boot Argument Buffer Size */ 85 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 86 87 #define CONFIG_CONS_INDEX 1 88 89 /* #define CONFIG_ENV_IS_NOWHERE */ 90 /* #define CONFIG_ENV_IS_IN_NAND */ 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_ENV_OFFSET 0x80000 93 #define CONFIG_ENV_SIZE 0x2000 94 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 95 96 #define CONFIG_SYS_MMC_ENV_DEV 0 97 #define CONFIG_SYS_MMC_ENV_PART 1 98 99 #ifdef CONFIG_ARM64 100 #define CPU_RELEASE_ADDR 0x80000000 101 #define COUNTER_FREQUENCY 50000000 102 #define CONFIG_GICV3 103 #define GICD_BASE 0x5fe00000 104 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 105 #define GICR_BASE 0x5fe40000 106 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 107 #define GICR_BASE 0x5fe80000 108 #endif 109 #else 110 /* Time clock 1MHz */ 111 #define CONFIG_SYS_TIMER_RATE 1000000 112 #endif 113 114 115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 116 #define CONFIG_SYS_NAND_MAX_CHIPS 2 117 #define CONFIG_SYS_NAND_ONFI_DETECTION 118 119 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 120 121 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 122 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 123 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 124 #else 125 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 126 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 127 #endif 128 129 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 130 131 #define CONFIG_SYS_NAND_USE_FLASH_BBT 132 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 133 134 /* USB */ 135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 136 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 137 #define CONFIG_FAT_WRITE 138 #define CONFIG_DOS_PARTITION 139 140 /* SD/MMC */ 141 #define CONFIG_SUPPORT_EMMC_BOOT 142 #define CONFIG_GENERIC_MMC 143 144 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 146 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 147 148 /* 149 * Network Configuration 150 */ 151 #define CONFIG_SERVERIP 192.168.11.1 152 #define CONFIG_IPADDR 192.168.11.10 153 #define CONFIG_GATEWAYIP 192.168.11.1 154 #define CONFIG_NETMASK 255.255.255.0 155 156 #define CONFIG_LOADADDR 0x84000000 157 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 158 159 #define CONFIG_CMDLINE_EDITING /* add command line history */ 160 161 #define CONFIG_BOOTCOMMAND "run $bootmode" 162 163 #define CONFIG_ROOTPATH "/nfs/root/path" 164 #define CONFIG_NFSBOOTCOMMAND \ 165 "setenv bootargs $bootargs root=/dev/nfs rw " \ 166 "nfsroot=$serverip:$rootpath " \ 167 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 168 "run __nfsboot" 169 170 #ifdef CONFIG_FIT 171 #define CONFIG_BOOTFILE "fitImage" 172 #define LINUXBOOT_ENV_SETTINGS \ 173 "fit_addr=0x00100000\0" \ 174 "fit_addr_r=0x84100000\0" \ 175 "fit_size=0x00f00000\0" \ 176 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 177 "bootm $fit_addr\0" \ 178 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 179 "bootm $fit_addr_r\0" \ 180 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 181 "bootm $fit_addr_r\0" \ 182 "__nfsboot=run tftpboot\0" 183 #else 184 #ifdef CONFIG_ARM64 185 #define CONFIG_BOOTFILE "Image" 186 #define LINUXBOOT_CMD "booti" 187 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 188 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 189 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 190 #else 191 #define CONFIG_BOOTFILE "zImage" 192 #define LINUXBOOT_CMD "bootz" 193 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 194 #define KERNEL_SIZE "kernel_size=0x00800000\0" 195 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 196 #endif 197 #define LINUXBOOT_ENV_SETTINGS \ 198 "fdt_addr=0x00100000\0" \ 199 "fdt_addr_r=0x84100000\0" \ 200 "fdt_size=0x00008000\0" \ 201 "kernel_addr=0x00200000\0" \ 202 KERNEL_ADDR_R \ 203 KERNEL_SIZE \ 204 RAMDISK_ADDR \ 205 "ramdisk_addr_r=0x84a00000\0" \ 206 "ramdisk_size=0x00600000\0" \ 207 "ramdisk_file=rootfs.cpio.uboot\0" \ 208 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 209 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 210 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 211 "setexpr kernel_size $kernel_size / 4 &&" \ 212 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 213 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 214 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 215 "run boot_common\0" \ 216 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 217 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 218 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 219 "run boot_common\0" \ 220 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 221 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 222 "tftpboot $fdt_addr_r $fdt_file &&" \ 223 "run boot_common\0" \ 224 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 225 "tftpboot $fdt_addr_r $fdt_file &&" \ 226 "setenv ramdisk_addr_r - &&" \ 227 "run boot_common\0" 228 #endif 229 230 #define CONFIG_EXTRA_ENV_SETTINGS \ 231 "netdev=eth0\0" \ 232 "verify=n\0" \ 233 "nor_base=0x42000000\0" \ 234 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 235 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 236 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 237 "tftpboot $tmp_addr u-boot.bin\0" \ 238 "emmcupdate=mmcsetn &&" \ 239 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 240 "tftpboot u-boot-spl.bin &&" \ 241 "mmc write $loadaddr 0 80 &&" \ 242 "tftpboot u-boot.bin &&" \ 243 "mmc write $loadaddr 80 780\0" \ 244 "nandupdate=nand erase 0 0x00100000 &&" \ 245 "tftpboot u-boot-spl.bin &&" \ 246 "nand write $loadaddr 0 0x00010000 &&" \ 247 "tftpboot u-boot.bin &&" \ 248 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 249 LINUXBOOT_ENV_SETTINGS 250 251 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 252 253 #define CONFIG_SYS_SDRAM_BASE 0x80000000 254 #define CONFIG_NR_DRAM_BANKS 2 255 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 256 #define CONFIG_SYS_MEM_TOP_HIDE 64 257 258 #if defined(CONFIG_ARM64) 259 #define CONFIG_SPL_TEXT_BASE 0x30000000 260 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 261 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 262 defined(CONFIG_ARCH_UNIPHIER_SLD8) 263 #define CONFIG_SPL_TEXT_BASE 0x00040000 264 #else 265 #define CONFIG_SPL_TEXT_BASE 0x00100000 266 #endif 267 268 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 269 #define CONFIG_SPL_STACK (0x30014c00) 270 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 271 #define CONFIG_SPL_STACK (0x3001c000) 272 #else 273 #define CONFIG_SPL_STACK (0x00100000) 274 #endif 275 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 276 277 #define CONFIG_PANIC_HANG 278 279 #define CONFIG_SPL_FRAMEWORK 280 #ifdef CONFIG_ARM64 281 #define CONFIG_SPL_BOARD_LOAD_IMAGE 282 #endif 283 284 #define CONFIG_SPL_BOARD_INIT 285 286 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 287 288 /* subtract sizeof(struct image_header) */ 289 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 290 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 291 292 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 293 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 294 #define CONFIG_SPL_MAX_SIZE 0x10000 295 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 296 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 297 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 298 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 299 #endif 300 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 301 302 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 303