xref: /openbmc/u-boot/include/configs/titanium.h (revision 8ccf98b1cfd2811e3121c719e294bdd8ebab1c45)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2b29ca4a1SStefan Roese /*
3b29ca4a1SStefan Roese  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
4b29ca4a1SStefan Roese  *
5b29ca4a1SStefan Roese  * Configuration settings for the ProjectionDesign / Barco
6b29ca4a1SStefan Roese  * Titanium board.
7b29ca4a1SStefan Roese  *
8b29ca4a1SStefan Roese  * Based on mx6qsabrelite.h which is:
9b29ca4a1SStefan Roese  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
10b29ca4a1SStefan Roese  */
11b29ca4a1SStefan Roese 
12b29ca4a1SStefan Roese #ifndef __CONFIG_H
13b29ca4a1SStefan Roese #define __CONFIG_H
14b29ca4a1SStefan Roese 
1502824dc7SEric Nelson #include "mx6_common.h"
16b29ca4a1SStefan Roese 
17b29ca4a1SStefan Roese #define CONFIG_MX6Q
18b29ca4a1SStefan Roese 
19cd7b6344STom Rini /* Provide the MACH_TYPE value that the vendor kernel requires. */
20cd7b6344STom Rini #define CONFIG_MACH_TYPE		3769
21b29ca4a1SStefan Roese 
22b29ca4a1SStefan Roese /* Size of malloc() pool */
23b29ca4a1SStefan Roese #define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
24b29ca4a1SStefan Roese 
25b29ca4a1SStefan Roese #define CONFIG_MXC_UART
26b29ca4a1SStefan Roese #define CONFIG_MXC_UART_BASE		UART1_BASE
27b29ca4a1SStefan Roese 
28b29ca4a1SStefan Roese /* I2C Configs */
29b089d039Strem #define CONFIG_SYS_I2C
30b089d039Strem #define CONFIG_SYS_I2C_MXC
3103544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
3203544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
33f8cb101eSYork Sun #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
34b29ca4a1SStefan Roese #define CONFIG_SYS_I2C_SPEED		100000
35b29ca4a1SStefan Roese 
36b29ca4a1SStefan Roese /* MMC Configs */
37b29ca4a1SStefan Roese #define CONFIG_SYS_FSL_ESDHC_ADDR	0
38b29ca4a1SStefan Roese #define CONFIG_SYS_FSL_USDHC_NUM	1
39b29ca4a1SStefan Roese 
40b29ca4a1SStefan Roese #define CONFIG_FEC_MXC
41b29ca4a1SStefan Roese #define IMX_FEC_BASE			ENET_BASE_ADDR
42b29ca4a1SStefan Roese #define CONFIG_FEC_XCV_TYPE		RGMII
43b29ca4a1SStefan Roese #define CONFIG_FEC_MXC_PHYADDR		4
44b29ca4a1SStefan Roese 
45b29ca4a1SStefan Roese /* USB Configs */
46b29ca4a1SStefan Roese #define CONFIG_MXC_USB_PORT	1
47b29ca4a1SStefan Roese #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
48b29ca4a1SStefan Roese #define CONFIG_MXC_USB_FLAGS	0
49b29ca4a1SStefan Roese 
50b29ca4a1SStefan Roese #define CONFIG_SYS_MEMTEST_START	0x10000000
51b29ca4a1SStefan Roese #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (500 << 20))
52b29ca4a1SStefan Roese 
535bc0543dSMario Six #define CONFIG_HOSTNAME			"titanium"
54b29ca4a1SStefan Roese #define CONFIG_UBI_PART			ubi
55b29ca4a1SStefan Roese #define CONFIG_UBIFS_VOLUME		rootfs0
56b29ca4a1SStefan Roese 
57b29ca4a1SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \
585bc0543dSMario Six 	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
59b29ca4a1SStefan Roese 	"kernel_fs=/boot/uImage\0"					\
60b29ca4a1SStefan Roese 	"kernel_addr=11000000\0"					\
615bc0543dSMario Six 	"dtb=" CONFIG_HOSTNAME "/"				\
625bc0543dSMario Six 		CONFIG_HOSTNAME ".dtb\0"			\
635bc0543dSMario Six 	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
64b29ca4a1SStefan Roese 	"dtb_addr=12800000\0"						\
65b29ca4a1SStefan Roese 	"script=boot.scr\0" \
66b29ca4a1SStefan Roese 	"uimage=uImage\0" \
67b29ca4a1SStefan Roese 	"console=ttymxc0\0" \
68b29ca4a1SStefan Roese 	"baudrate=115200\0" \
69b29ca4a1SStefan Roese 	"fdt_high=0xffffffff\0"	  \
70b29ca4a1SStefan Roese 	"initrd_high=0xffffffff\0" \
71b29ca4a1SStefan Roese 	"mmcdev=0\0" \
72b29ca4a1SStefan Roese 	"mmcpart=1\0" \
73b29ca4a1SStefan Roese 	"uimage=uImage\0" \
74b29ca4a1SStefan Roese 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
75b29ca4a1SStefan Roese 		" ${script}\0" \
76b29ca4a1SStefan Roese 	"bootscript=echo Running bootscript from mmc ...; source\0" \
77b29ca4a1SStefan Roese 	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
78b29ca4a1SStefan Roese 	"mmcroot=/dev/mmcblk0p2\0" \
79b29ca4a1SStefan Roese 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
80b29ca4a1SStefan Roese 		"root=${mmcroot} rootwait rw\0" \
81b29ca4a1SStefan Roese 	"bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
82b29ca4a1SStefan Roese 		" ${uimage}; bootm\0" \
83b29ca4a1SStefan Roese 	"addip=setenv bootargs ${bootargs} "				\
84b29ca4a1SStefan Roese 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
85b29ca4a1SStefan Roese 		":${hostname}:${netdev}:off panic=1\0"			\
86b29ca4a1SStefan Roese 	"addcon=setenv bootargs ${bootargs} console=ttymxc0,"		\
87b29ca4a1SStefan Roese 		"${baudrate}\0"						\
88b29ca4a1SStefan Roese 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
89b29ca4a1SStefan Roese 	"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0"	\
90b29ca4a1SStefan Roese 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
91b29ca4a1SStefan Roese 		"nfsroot=${serverip}:${rootpath}\0"			\
925bc0543dSMario Six 	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
93b29ca4a1SStefan Roese 	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
94b29ca4a1SStefan Roese 	"boot_vol=0\0"							\
95b29ca4a1SStefan Roese 	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
96b29ca4a1SStefan Roese 	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
97b29ca4a1SStefan Roese 	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
98b29ca4a1SStefan Roese 		" ${filesize}\0"					\
99b29ca4a1SStefan Roese 	"upd_ubifs=run load_ubifs update_ubifs\0"			\
100b29ca4a1SStefan Roese 	"init_ubi=nand erase.part ubi;ubi part ${part};"		\
101b29ca4a1SStefan Roese 		"ubi create ${vol} c800000\0"				\
10243ede0bcSTom Rini 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
10343ede0bcSTom Rini 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
104b29ca4a1SStefan Roese 	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
105b29ca4a1SStefan Roese 		" addcon addmtd;"					\
106b29ca4a1SStefan Roese 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
107b29ca4a1SStefan Roese 	"ubifsargs=set bootargs ubi.mtd=ubi "				\
108b29ca4a1SStefan Roese 		"root=ubi:rootfs${boot_vol} rootfstype=ubifs\0"		\
109b29ca4a1SStefan Roese 	"ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0"	\
110b29ca4a1SStefan Roese 	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
111b29ca4a1SStefan Roese 		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
112b29ca4a1SStefan Roese 	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
113b29ca4a1SStefan Roese 		"addmtd;bootm ${kernel_addr} - ${dtb_addr}\0"		\
114b29ca4a1SStefan Roese 	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
115b29ca4a1SStefan Roese 	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
116b29ca4a1SStefan Roese 	"net_nfs=run load_dtb load_kernel; "				\
117b29ca4a1SStefan Roese 		"run nfsargs addip addcon addmtd;"			\
118b29ca4a1SStefan Roese 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
119b29ca4a1SStefan Roese 	"delenv=env default -a -f; saveenv; reset\0"
120b29ca4a1SStefan Roese 
121b29ca4a1SStefan Roese #define CONFIG_BOOTCOMMAND		"run nand_ubifs"
122b29ca4a1SStefan Roese 
123b29ca4a1SStefan Roese /* Physical Memory Map */
124b29ca4a1SStefan Roese #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
125b29ca4a1SStefan Roese #define PHYS_SDRAM_SIZE			(512 << 20)
126b29ca4a1SStefan Roese 
127b29ca4a1SStefan Roese #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
128b29ca4a1SStefan Roese #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
129b29ca4a1SStefan Roese #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
130b29ca4a1SStefan Roese 
131b29ca4a1SStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET \
132b29ca4a1SStefan Roese 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
133b29ca4a1SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR \
134b29ca4a1SStefan Roese 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
135b29ca4a1SStefan Roese 
136b29ca4a1SStefan Roese /* Enable NAND support */
137b29ca4a1SStefan Roese #ifdef CONFIG_CMD_NAND
138b29ca4a1SStefan Roese 
139b29ca4a1SStefan Roese /* NAND stuff */
140b29ca4a1SStefan Roese #define CONFIG_SYS_MAX_NAND_DEVICE	1
141b29ca4a1SStefan Roese #define CONFIG_SYS_NAND_BASE		0x40000000
142b29ca4a1SStefan Roese #define CONFIG_SYS_NAND_5_ADDR_CYCLE
143b29ca4a1SStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION
144b29ca4a1SStefan Roese 
145b29ca4a1SStefan Roese /* DMA stuff, needed for GPMI/MXS NAND support */
146b29ca4a1SStefan Roese 
147b29ca4a1SStefan Roese /* Environment in NAND */
148b29ca4a1SStefan Roese #define CONFIG_ENV_OFFSET		(16 << 20)
149b29ca4a1SStefan Roese #define CONFIG_ENV_SECT_SIZE		(128 << 10)
150b29ca4a1SStefan Roese #define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
151b29ca4a1SStefan Roese #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + (512 << 10))
152b29ca4a1SStefan Roese #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
153b29ca4a1SStefan Roese 
154b29ca4a1SStefan Roese #else /* CONFIG_CMD_NAND */
155b29ca4a1SStefan Roese 
156b29ca4a1SStefan Roese /* Environment in MMC */
157b29ca4a1SStefan Roese #define CONFIG_ENV_SIZE			(8 << 10)
158b29ca4a1SStefan Roese #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
159b29ca4a1SStefan Roese #define CONFIG_SYS_MMC_ENV_DEV		0
160b29ca4a1SStefan Roese 
161b29ca4a1SStefan Roese #endif /* CONFIG_CMD_NAND */
162b29ca4a1SStefan Roese 
163b29ca4a1SStefan Roese /* UBI/UBIFS config options */
164b29ca4a1SStefan Roese 
165b29ca4a1SStefan Roese #endif			       /* __CONFIG_H */
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